Interleaver address generator and method of generating an...

Details Interleaver address generator and method of generating an... Interleaver address generator and method of generating an...

2006-06-06

2006-06-06

Chung, Phung My (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C711S218000

Reexamination Certificate

active

07058874

ABSTRACT:
An interleaver circuit architectures, which utilizes the relationship between intra-row elements in a matrix, in order to simplify the MOD computations necessary in an interleaver. The interleaver calculates a subset of results, stores those results, performs operations on the stored results in order to obtain new results, then updates at least some of the old results with the new results for the next column operation. The interleaver address is then calculated row by row. By storing only a subset of the results and replacing old results with new results, the interleaver can calculate the interleaver address “on the fly” in one clock cycle with very little delay. The interleaver may also require less power and smaller substrate surface area.

REFERENCES:
patent: 6631491 (2003-10-01), Shibutani et al.
patent: 1 1871339 (2002-03-01), None

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