Interleaved track and hold circuit

Details Interleaved track and hold circuit Interleaved track and hold circuit

2007-08-22

2009-06-09

Williams, Howard (Department: 2819)

Coded data generation or conversion

Sample and hold

C327S091000, C327S094000

Reexamination Certificate

active

07545296

ABSTRACT:
The invention relates to an interleaved track and hold circuit for tracking and holding a value of a continuous input signal and to provide discrete values thereof, wherein the circuit comprises a first and a second stage. To avoid tones caused by differences in the non-ideal elements when switching through several parallel second stages the circuit according to the invention comprises a single first stage and at least two second stages.

REFERENCES:
patent: 4404479 (1983-09-01), Toyomaki
patent: 7015729 (2006-03-01), Tursi et al.
patent: 2006/0055575 (2006-03-01), Van Tuijl
patent: WO 2004066504 (2004-08-01), None
Black, W.C. and Hodges, D.A., “Time interleaved converter arrays,” IEEE Journal of Solid-State Circuits, vol. 15, Issue 6, pp. 1022-1029, Dec. 1980.
Elbornsson, J. et al., “Blind equalization of time errors in a time-interleaved ADC system,” IEEE Transactions on Signal Processing, vol. 53, Issue 4, pp. 1413-1424, Apr. 2005.
Kurosawa, N. et al., “Explicit analysis of channel mismatch effects in time-interleaved ADC systems,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 48, Issue 3, pp. 261-271, Mar. 2001.
Leger, G. et al., “Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, Issue 1, pp. 140-150, Jan. 2004.
Lim, P.J. and Wooley, B.A., “A high-speed sample-and-hold technique using a Miller hold capacitance,” IEEE Journal of Solid-State Circuits, vol. 26, Issue 4, pp. 643-651, Apr. 1991.

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