Interleaved mirrored memory systems

Details Interleaved mirrored memory systems Interleaved mirrored memory systems

2006-10-31

2006-10-31

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230040, C711S005000, C711S114000, C711S153000, C711S157000, C711S169000, C711S173000

Reexamination Certificate

active

07130229

ABSTRACT:
In some embodiments, a system includes a first memory assembly coupled to a first channel and a second memory assembly coupled to a second channel. The system includes a memory controller to write first and second primary data sections to the first and second memory assemblies, respectively, and write first and second redundant data sections to the second and first memory assemblies, respectively, wherein the first and second redundant data sections are redundant with respect to the first and second primary data sections, respectively. Other embodiments are described and claimed.

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