Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration – Loading initialization program
Reexamination Certificate
2007-12-04
2007-12-04
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
Loading initialization program
C713S001000
Reexamination Certificate
active
11010167
ABSTRACT:
A flash memory has an interleaved boot block compatible with multiple processor architectures. The interleaved boot block may include one boot block compatible with a first CPU architecture and another boot block compatible with a second CPU architecture. These two boot blocks may be combined in an interleaved manner in the flash memory so that during a boot process only one of the two boot blocks executes, although both are stored in the flash memory. By interleaving different boot blocks, a common socket computer system capable of supporting multiple processor architectures may be achieved without fully replacing an incompatible basic input/output system (BIOS). Further, the flash memory may contain an updatable portion in which any BIOS segments incompatible with a processor architecture may be updated via a recovery, or update, process.
REFERENCES:
patent: 5694600 (1997-12-01), Khenson et al.
patent: 5704035 (1997-12-01), Shipman
patent: 5844986 (1998-12-01), Davis
patent: 5890191 (1999-03-01), Espinor et al.
patent: 5991197 (1999-11-01), Ogura et al.
patent: 6003130 (1999-12-01), Anderson
patent: 6009495 (1999-12-01), DeRoo et al.
patent: 6031757 (2000-02-01), Chuang et al.
patent: 6058048 (2000-05-01), Kwon
patent: 6081664 (2000-06-01), Nowlin, Jr.
patent: 6081890 (2000-06-01), Datta
patent: 6154819 (2000-11-01), Larsen et al.
patent: 6154837 (2000-11-01), Fudeyasu et al.
patent: 6182187 (2001-01-01), Cox et al.
patent: 6205548 (2001-03-01), Hasbun
patent: 6272629 (2001-08-01), Stewart
patent: 6367074 (2002-04-01), Bates et al.
patent: 6381693 (2002-04-01), Fish et al.
patent: 6463535 (2002-10-01), Drews
patent: 6633964 (2003-10-01), Zimmer et al.
patent: 2004/0210750 (2004-10-01), Chheda et al.
Intel Itanium Architecture Software Developer's Manual, Processor Abstraction Layer, Chapter 11 (2002).
Extensible Firmware Interface Specification, EFI Byte Virtual Machine, Chapter 19 (2002).
IA-32 Intel Architecture Software Developer's Manual, Multiple-Processor Management, Chapter 7 (2004).
Intel 82802AB/82802AC Firmware Hub (FWH) Datasheet—May (2000).
Bulusu Mallik
Khanna Rahul
Zimmer Vincent J.
Marshall & Gerstein & Borun LLP
Perveen Rehana
Steynov Stefan
LandOfFree
Interleaved boot block to support multiple processor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interleaved boot block to support multiple processor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interleaved boot block to support multiple processor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3844439