Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-06-12
2008-11-04
Everhart, Caridad M (Department: 2895)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S588000, C438S129000, C257S773000, C257SE21627, C257SE21641
Reexamination Certificate
active
07446038
ABSTRACT:
An interlayer interconnect structure of a three-dimensional memory includes memory cell groups, each composed of a plurality of memory cells and connected to their respective selection transistors, because of special arrangement of lines and first plugs as well as line layouts. The line layouts involve disposing a plurality of lines on each of a plurality of horizontal levels, and selectively forming second plugs between adjoining lines disposed on upper and lower horizontal levels, such that the plugs selectively connect the adjoining upper and lower lines to each other. Since identical layout patterns are adopted in individual stacking states of stacking layers disposed in the three-dimensional memory, the upper lines and the lower lines of the stacking layers of the three-dimensional memory share the same layouts, leading to a reduction in the number of masks used, simpler process adjustment, and lower costs.
REFERENCES:
patent: 6501127 (2002-12-01), Mori
patent: 6984861 (2006-01-01), Yamada et al.
patent: 2005/0127519 (2005-06-01), Scheuerlein et al.
patent: 2005/0133875 (2005-06-01), Zhang
patent: 2004-362753 (2004-12-01), None
Everhart Caridad M
Industrial Technology Research Institute
King Anthony
WPAT, P.C.
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