Interlayer dielectric under stress for an integrated circuit

Details Interlayer dielectric under stress for an integrated circuit Interlayer dielectric under stress for an integrated circuit

2007-07-03

2007-07-03

Baumeister, B. William (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S903000, C257SE27098

Reexamination Certificate

active

11100168

ABSTRACT:
An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.

REFERENCES:
patent: 7019369 (2006-03-01), Sato
patent: 2004/0159905 (2004-08-01), Sato
H. S. Yang, Dual Stress Liner for High Performance sub-45nm Gate Length SOI CMOS Manufacturing.
Shinya Ito, Mechanical Stress Effect of Etch-Stop Nitride and Its Impact on Deep Submicron Transistor Design.

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