Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2008-07-01
2011-10-11
Richards, N Drew (Department: 2895)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C257S369000
Reexamination Certificate
active
08034726
ABSTRACT:
By forming a buffer material above differently stressed contact etch stop layers followed by the deposition of a further stress-inducing material, enhanced overall device performance may be accomplished, wherein an undesired influence of the additional stress-inducing layer may be reduced in device regions, for instance, by removing the additional material or by performing a relaxation implantation process. Furthermore, process uniformity during a patterning sequence for forming contact openings may be enhanced by partially removing the additional stress-inducing layer at an area at which a contact opening is to be formed.
REFERENCES:
patent: 6436747 (2002-08-01), Segawa et al.
patent: 6953728 (2005-10-01), Murakami et al.
patent: 7060549 (2006-06-01), Craig et al.
patent: 7190033 (2007-03-01), Chang et al.
patent: 7470618 (2008-12-01), Sayama et al.
patent: 2004/0198002 (2004-10-01), Murakami et al.
patent: 2005/0118765 (2005-06-01), Taniguchi et al.
patent: 2005/0214998 (2005-09-01), Chen et al.
patent: 2005/0218455 (2005-10-01), Maeda et al.
patent: 2005/0260806 (2005-11-01), Chang et al.
patent: 2006/0223290 (2006-10-01), Belyansky et al.
patent: 2007/0010073 (2007-01-01), Chen et al.
patent: 2007/0122966 (2007-05-01), Hoentschel et al.
patent: 2008/0124858 (2008-05-01), Nguyen et al.
patent: 2008/0303090 (2008-12-01), Ieong et al.
patent: 102005057074 (2007-05-01), None
patent: 102007052051 (2009-05-01), None
patent: 02201922 (1990-08-01), None
patent: WO 2007/126807 (2007-11-01), None
patent: WO 2008/016505 (2008-02-01), None
Translation of Official Communication from German Patent Office for German Patent Application No. 10 2007 063 230.6-33 dated Sep. 21, 2009.
Finken Michael
Hohage Joerg
Richter Ralf
Salz Heike
Advanced Micro Devices , Inc.
Richards N Drew
Sun Yu-Hsi
Williams Morgan & Amerson P.C.
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