Interlayer dielectric material in a semiconductor device...

Details Interlayer dielectric material in a semiconductor device... Interlayer dielectric material in a semiconductor device...

2011-01-25

2011-01-25

Richards, N Drew (Department: 2895)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C257S369000

Reexamination Certificate

active

07875561

ABSTRACT:
A highly stressed dielectric material, such as a tensile stressed material, may be deposited in a conformal manner so as to respect any deposition constraints caused by pronounced surface topography of highly scaled semiconductor devices, followed by the deposition of a buffer material having enhanced gap-filling capabilities. Thereafter, a further stress-inducing layer is deposited to form a doublet structure, which acts on the transistor elements, thereby enhancing overall performance, without increasing the probability of creating deposition-related irregularities. Hence, production yield as well as performance of highly scaled semiconductor devices may be increased.

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Translation of Official Communication from German Patent Office for German Patent Application No. 10 2007 063 272.1-33 dated Sep. 7, 2009.
Translation of Official Communication from German Patent Office for German Patent Application No. 10 2007 063 272.1 dated Oct. 24, 2008.

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