Interlayer contact for use in a static RAM cell

Details Interlayer contact for use in a static RAM cell Interlayer contact for use in a static RAM cell

1984-05-24

1986-04-08

Hearn, Brian E.

Metal treatment

Stock

Ferrous

29571, 29576J, 29590, 357 42, 357 71, 357 59, 148DIG19, 148DIG147, 148DIG164, H01L 2710, H01L 2904, H01L 2190

Patent

active

045816239

ABSTRACT:
A CMOS static RAM, which has P channel transistors formed in a second polysilicon layer, N channel transistors formed in the substrate, and gates of both the N channel and P channel transistors formed in a first polysilicon layers, requires that ohmic contact be made between semiconductor material of differing conductivity type. The first polysilicon layer is N-type, and the second polysilicon layer is P-type. Ohmic contact therebetween is achieved by providing a silicide layer which is between these two layers and in physical contact with both. Ohmic contact between N-type regions in the substrate and the second polysilicon layer is similarly achieved by sandwiching silicide therebetween.

REFERENCES:
patent: 4378628 (1983-04-01), Levinstein et al.
patent: 4398335 (1983-08-01), Lehrer
patent: 4467518 (1984-08-01), Bansal et al.

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