Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-12-27
2005-12-27
Baumeister, B. William (Department: 2891)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S624000, C438S668000, C438S637000, C438S667000, C257S773000, C257S775000, C257S765000, C257S750000, C257S758000, C257S760000
Reexamination Certificate
active
06979643
ABSTRACT:
In a method for forming interlayer connections, metal conducting paths in an overlaying layer and vias forming the deposit in one and the same operation. In an interlayer connection formed in this manner the vias are provided integral with connecting conducting paths in the overlaying layer.
REFERENCES:
patent: 5322816 (1994-06-01), Pinter
patent: 6127070 (2000-10-01), Yang et al.
patent: 6200855 (2001-03-01), Lee
patent: 6307267 (2001-10-01), Wada et al.
patent: 6342416 (2002-01-01), Kim et al.
patent: 6373136 (2002-04-01), Otsuka et al.
patent: 6417572 (2002-07-01), Chidambarrao et al.
patent: 6501113 (2002-12-01), Tsunemine et al.
patent: 6555450 (2003-04-01), Park et al.
patent: 6600225 (2003-07-01), Tanaka
patent: 05160445 (1993-06-01), None
Carlsson Johan
Dyreklev Peter
Gustafsson Goran
Anya Igwe U.
Baumeister B. William
Jacobson & Holman PLLC
Thin Film Electronics ASA
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