Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2010-01-19
2010-12-28
Dickey, Thomas L (Department: 2893)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257SE21579, C257SE21269, C427S096800, C427S058000
Reexamination Certificate
active
07858510
ABSTRACT:
Protective caps residing at an interface between metal lines and dielectric diffusion barrier (or etch stop) layers are used to improve electromigration performance of interconnects. Protective caps are formed by depositing a first layer of aluminum-containing material over an exposed copper line by treating an oxide-free copper surface with an organoaluminum compound in an absence of plasma at a substrate temperature of at least about 350° C. The formed aluminum-containing layer is passivated either partially or completely in a chemical conversion which forms Al—N, Al—O or both Al—O and Al—N bonds in the layer. Passivation is performed in some embodiments by contacting the substrate having an exposed first layer with an oxygen-containing reactant and/or nitrogen-containing reactant in the absence of plasma. Protective caps can be formed on substrates comprising exposed ULK dielectric. The aluminum-containing layer residing on the dielectric portion will typically spontaneously form non-conductive layer comprising Al—O bonds.
REFERENCES:
patent: 4282268 (1981-08-01), Priestley et al.
patent: 6143657 (2000-11-01), Liu et al.
patent: 6181013 (2001-01-01), Liu et al.
patent: 6271595 (2001-08-01), McGahay et al.
patent: 6750541 (2004-06-01), Ohtsuka et al.
patent: 6821890 (2004-11-01), McGahay et al.
patent: 6855645 (2005-02-01), Tang et al.
patent: 6974768 (2005-12-01), Kailasam
patent: 7060619 (2006-06-01), Cowley et al.
patent: 7202185 (2007-04-01), Hausmann et al.
patent: 7211509 (2007-05-01), Gopinath et al.
patent: 7239017 (2007-07-01), Yu et al.
patent: 7247946 (2007-07-01), Bruley et al.
patent: 7282438 (2007-10-01), Yu et al.
patent: 7297608 (2007-11-01), Papasouliotis et al.
patent: 7396759 (2008-07-01), Van Schravendijk et al.
patent: 7576006 (2009-08-01), Yu et al.
patent: 7420275 (2009-09-01), Yu et al.
patent: 7648899 (2010-01-01), Banerji et al.
patent: 7727880 (2010-06-01), Chattopadhyay et al.
patent: 7727881 (2010-06-01), Chattopadhyay et al.
patent: 2001/0006701 (2001-07-01), Kobayashi et al.
patent: 2002/0066411 (2002-06-01), Chiang et al.
patent: 2002/0155702 (2002-10-01), Aoki et al.
patent: 2003/0209738 (2003-11-01), Ohto et al.
patent: 2004/0097075 (2004-05-01), Bradshaw et al.
patent: 2004/0238963 (2004-12-01), Fujisawa
patent: 2006/0046479 (2006-03-01), Rajagopalan et al.
patent: 2007/0035029 (2007-02-01), Caubet et al.
patent: 2007/0037388 (2007-02-01), Hohage et al.
patent: 2007/0105377 (2007-05-01), Koos et al.
patent: 2000-252278 (2000-09-01), None
U.S. Appl. No. 11/710,652, filed Feb. 22, 2007, Entitled: “Improved Diffusion Barrier And Etch Stop Films”.
Office Action dated Jun. 13, 2007, Novellus Systems, Inc., van Schravendijk et al., “Protection of CU Damascene Interconnects by Formation of a Self-Aligned Buffer Layer” U.S. Appl. No. 10/980,076, filed Nov. 3, 2004.
Renesas Technology Corp., Japan, “Reliability Improvement and its Mechanism for Cu Interconnects with Cu-Al Alloy Seeds”, pp. 77 & 78 (ADMENTA 2006).
IEEE 07CH37867 45thAnnual International Reliability Physics Symposium, Phoenix, 2007, NEC Electronics Corporation, Japan “Analytical Study of Impurity Doping Effects on Electromigration of Cu Interconnects by Employing Comprehensive Scattering Model”, pp. 117-121.
IEEE © 2004, Taiwan Semiconductor Manufacturing Company, Ltd., “High Performanc Cu interconnects capped with Full-Coverage ALD TaNx layer for Cu/Low-k (k˜2.5) Metallization”, pp. 72-74.
IEEE © 2005, NEC Corporation and NEC Electronics, Japan, A Robust 45 nm-node, Dual Damascene Interconnects with High Quality Cu/barrier Interface by a Novel Oxygen Absorption Process (4) four pages.
U.S. Office Action, mailed Nov. 28, 2007, for U.S. Appl. No. 10/980,076.
U.S. Office Action, mailed Aug. 21, 2008 for U.S. Appl. No. 11/888,323.
U.S. Office Action, mailed Apr. 2, 2009 for U.S. Appl. No. 12/074,108.
Notice of Allowance and Fee Due mailed Jun. 17, 2009 for U.S. Appl. No. 11/888,323 and Allowed Claims.
U.S. Office Action mailed Sep. 1, 2009 for U.S. Appl. No. 11/709,293.
U.S. Office Action mailed Sep. 4, 2009 for U.S. Appl. No. 11/709,294.
Novellus Systems, Inc., Banerji et al., “Interfacial Layers for Electromigration Resistance Improvement in Damascene Interconnect” U.S. Appl. No. 12/630,457, filed Dec. 3, 2009.
U.S. Notice of Allowance and Fee Due, mailed Sep. 4, 2009, for U.S. Appl. No. 12/074,108 and Allowed Claims.
U.S. Notice of Allowance and Allowed Claims mailed Jan. 29, 2010 for U.S. Appl. No. 11/709,293.
U.S. Notice of Allowance and Allowed Claims mailed Feb. 22, 2010 for U.S. Appl. No. 11/709,294.
Novellus Systems, Inc., Chattopadhyay et al., “Protective Self-Aligned Buffer Layers for Damascene Interconnects”, U.S. Appl. No. 12/762,223, filed Apr. 16, 2010.
Novellus Systems, Inc., Chattopadhyay et al., “Protective Self-Aligned Buffer Layers for Damascene Interconnects”, U.S. Appl. No. 12/763,545, filed Apr. 20, 2010.
Novellus Systems, Inc. Yu et al., “Interfacial Capping Layers For Interconnects”, U.S. Appl. No. 12/688,154, filed Jan. 15, 2010.
Novellus Sytstems, Inc., Yu et al., “Protective Self-Aligned Buffer Layers for Damascene Interconnects”, U.S. Appl. No. 12/693,645, filed Jan. 26, 2010.
U.S. Notice of Allowance and Allowed Claims, mailed Jun. 28, 2010, for U.S. Appl. No. 12/630,457 and Allowed Claims.
Antonelli George Andrew
Banerji Ananda
O'loughlin Jennifer
Schravendijk Bart van
Sriram Mandyam
Dickey Thomas L
Novellus Systems Inc.
Weaver Austin Villeneuve & Sampson LLP
Yushin Nikolay
LandOfFree
Interfacial layers for electromigration resistance... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interfacial layers for electromigration resistance..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interfacial layers for electromigration resistance... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4158831