Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-01-02
2003-09-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
Reexamination Certificate
active
06620713
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention directs to a semiconductor device and methods of fabricating the same. Specifically, the present invention directs to methods and apparatuses of fabricating a metal-oxide-semiconductor (MOS) transistor comprising a hydrogen-free silicon interfacial layer between a high-k gate dielectric layer and a silicon gate electrode and a MOS transistor comprising a hydrogen-free gate electrode.
2. Discussion of Related Art
Electronic circuits are often manufactured as integrated circuits in and on semiconductor wafers. An integrated circuit includes many interconnected electronic components, such as transistors, diodes, capacitors and other devices, which are manufactured in and on the semiconductor wafer.
FIG. 1A
illustrates a conventional metal-oxide-semiconductor (MOS) transistor
100
, which are manufactured on a semiconductor substrate
112
. Transistor
100
includes a gate oxide layer
104
and a gate electrode
106
, typically made of polysilicon, on the gate oxide layer
104
. Spacers
108
are usually formed on opposing sides of the gate electrode
106
. The substrate
102
is generally P or N doped silicon depending on whether a p-type of n-type transistor is to be formed on the substrate
102
. The substrate includes source and drain regions
110
which are of opposite doping to the rest of the substrate
102
. The source and drain regions
110
are usually manufactured by ion implantation of dopants respectively after the gate electrode and after the spacers
108
are formed.
Silicon dioxide, silicon oxynitride, and nitrided oxides films are typical examples of materials used for the gate oxide layer
104
. This layer prevents current from flowing between the gate electrode
106
and the source/drain regions
110
or channel region
105
in electronic devices (e.g., the MOS transistor
100
). This is typically used in a MOS field-effect transistor (MOSFET).
Current demands for thinner and smaller products require increase density of devices on a semiconductor chip that are faster and consuming less power. There are thus demands for scaling down the devices in all dimension, lateral and vertical, to achieve adequate device performance. The vertical scaling down involves making all of the layers in the electronic devices as thin as possible. Alternatively, it also is established that to drive current into the MOS transistor, the gate oxide is made as thin as possible. Silicon oxide has been the preferred gate dielectric material, however, silicon oxide cannot be made so thin that it would compromise the performance and functionality of the electronic devices (e.g., lost of function due to charge leakage). The limitation for the thickness of the silicon oxide is the oxide breakdown and the reliability of the process and the technology being used to form a uniform and thin silicon oxide. It has been one practice to substitute the silicon dioxide layer with a higher permittivity gate dielectric since a high permittivity layer
114
can be made thinner and still maintain a high dielectric characteristic. (See FIG.
1
B). The materials used to form the high permittivity gate dielectric
114
are referred to as high-k dielectric materials (high dielectric constants).
Most high-k gate dielectric materials however, are not compatible with crystalline silicon or polycrystalline silicon (polysilicon) gate electrodes. In order to switch to the high-k gate dielectric
114
, many manufacturers have replaced the conventional polysilicon gate electrode
106
with a metal gate electrode
116
(see FIG.
1
B). One problem with metal gate electrode
116
is a complex fabrication process is required to make the device due to the workfunction requirement.
It is well known that many different electronic devices are often manufactured on the same substrate
102
. One example of an integration of many electronic devices on the same wafer substrate is a complimentary metal oxide semiconductor (CMOS) device, in which an n-type MOS (NMOS) and a p-type MOS (PMOS) are made on the same silicon wafer substrate. It is known that the threshold voltage of a CMOS device is a critical parameter for the proper functioning of the electronic devices. Proper workfunctions are among the necessary factors to ensure that the threshold voltage is achieved. The metal gate electrode
116
for the CMOS device thus, will need to have workfunctions that match both the PMOS and the NMOS devices. One metal is typically insufficient to satisfy that requirement. Thus, with the metal gate electrode
116
, additional processing steps are required to obtain the correct threshold voltage.
For example, a metal film
1
is used to make the gate electrode having a correct workfunction for the NMOS
120
and a metal film
2
is used to make the gate electrode having a correct workfunction for the PMOS
122
. (See FIG.
1
C). Use of a dual film deposition severely complicates integration. With the metal gate electrode, it is thus, complicated and difficult to make both the NMOS and the PMOS on the same substrate.
There is thus a need to have an electronic device having the high-k gate dielectric layer that is compatible with the silicon or polysilicon gate electrode.
REFERENCES:
patent: 4084024 (1978-04-01), Schumacher
patent: 4481229 (1984-11-01), Suzuki et al.
patent: 4987102 (1991-01-01), Nguyen et al.
patent: 5750211 (1998-05-01), Weise et al.
patent: 6432763 (2002-08-01), Yu
patent: 6451641 (2002-09-01), Halliyal et al.
Arghavani Reza
Chau Robert
Doczy Mark
Roberds Brian
Hoang Quoc
Nelms David
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