Interface void monitoring in a damascene process

Details Interface void monitoring in a damascene process Interface void monitoring in a damascene process

2002-04-11

2004-04-06

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

C438S015000, C438S016000

Reexamination Certificate

active

06716650

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to a method of monitoring voids in damascene and dual damascene structures.
2. Description of the Related Art
The need for high performance semiconductor chips has continued to increase over the past several years, while at the same time the functionality of the circuitry has become more complex and the amount of area per chip has decreased. One approach to increase the speed and performance of the semiconductor chip is to reduce the size of the individual integrated circuit components. In modem integrated circuits, the channel length, and thus the gate length, of a typical field effect transistor (FET) is scaled down to a size of 0.2 &mgr;m and less to reduce the switching speed of the FET elements sufficiently in order to allow, for example, a central processing unit (CPU) to operate with clock frequencies of up to 1 GHz and above. With small feature sizes, the performance of the semiconductor chips is not only limited by the switching speed of individual FET elements, but also by the electrical conductivity of the metal interconnects electrically connecting the various individual components and by the parasitic capacitances associated with the metal interconnects. In order to take full advantage of transistor elements capable of operating at fast speeds and exhibiting smaller feature sizes, the metal interconnects must be highly conductive and/or the parasitic capacitance between adjacent interconnect lines or vias should be kept as low as possible.
A typical process for surface wiring the individual components of an integrated circuit, also referred to as “metallization,” is the so-called damascene process in which trenches and/or vias are formed in an insulating layer and are subsequently filled with a conductive material to form the conductive lines interconnecting the individual components of the integrated circuit. Currently, most of the silicon-based semiconductor chips comprise a metallization layer including silicon dioxide as a dielectric material and aluminum as the conductive material due to aluminum's excellent adhesion to the surrounding silicon dioxide without any tendency to diffuse into the silicon dioxide. For integrated circuits having critical feature sizes of 0.5 &mgr;m and less, the so-called interconnect delay caused by the limited conductivity of the metal lines and the relatively high dielectric constant of the silicon dioxide begins to dominate the switching speed of individual semiconductor elements. Thus, great efforts have been made to replace the metal and/or the dielectric by an appropriate material so as to reduce the RC constant defined by the resistance of the conductive lines and the parasitic capacitance between adjacent lines.
Among various materials, copper has been proven to be one promising candidate for replacing the aluminum, due to its lower specific resistance which is about one order of magnitude smaller than that of aluminum. Moreover, contrary to aluminum, copper does not show eutectic reactions and thermally-induced electromigration when used in very large scale integration (“VLSI”) and ultra-large scale integration (“ULSI”) semiconductor chips. Additionally, copper is capable of being deposited at low temperatures with high aspect ratios, thereby yielding a good step coverage.
As previously explained, in order to provide a highly reliable integrated circuit, the metal of the interconnect lines has to sufficiently adhere to the surrounding dielectric material, and diffusion of the metal atoms into the dielectric material must be reduced as much as possible. Thus, in many cases, the metal may not be directly deposited onto the dielectric material. Instead, a barrier layer is deposited on the surface of the dielectric layer prior to deposition of the metal. For example, copper readily diffuses into silicon dioxide and does not sufficiently adhere to silicon dioxide. Accordingly, a thin barrier layer is deposited to provide for sufficient adhesion of the copper and to prevent diffusion of the copper into the silicon dioxide.
Tantalum is an attractive barrier material because of its high melting point and immiscibility with copper. Furthermore, it provides a low-resistance ohmic contact and excellent adhesion to copper. Doping the tantalum with nitrogen blocks grain boundary diffusion paths. Therefore, tantalum nitride, for instance deposited by reactive sputtering of tantalum in the presence of nitrogen, can also be used as a barrier layer. Therefore, titanium nitride is also well-suited as a barrier material. These layers can be deposited by sputtering or CVD (chemical vapor deposition).
In the damascene process for forming a metallization layer comprising, for example, silicon dioxide and copper, the generation of voids at the interface of the dielectric and the conductive material, especially at the bottom of vias formed in the dielectric on top of a preceding metallization layer, is a particularly serious issue. Furthermore, it was confirmed by different investigations that interface voids are generated between the barrier metal, e.g., tantalum or tantalum nitride, and the underlying copper. Such interface voids can be a result of an insufficient heat dissipation during sputtering and can form when the copper thermally contracts upon cooling after deposition. Thus, the damascene process has to be continuously monitored to obtain a required level of reliability of the integrated circuit.
With reference to
FIG. 1
, a typical prior art damascene process and a method of monitoring via voids will briefly be discussed. Reference number
1
denotes a standard damascene structure. A substrate
2
, such as a silicon substrate or any other substrate appropriate for semiconductor or integrated circuit technology, may include various layers defining semiconductor elements, such as field effect transistors (FETs) (not shown). The substrate
2
is at least partially covered with a dielectric material, such as silicon dioxide (SiO
2
), as a first insulating layer
3
. Openings
9
are formed in the insulating layer
3
. The openings
9
are filled with a metal, such as copper, tungsten or aluminum. The openings
9
are separated from each other and may form individual metal islands and/or metal lines of a first metallization layer.
The metal lines and/or islands will commonly be referred to as metal regions
4
. Over the first insulating layer
3
and the metal regions
4
a second insulating layer
5
is located that comprises vias
7
in registration to the metal regions
4
. A barrier layer
6
comprising, for example, tantalum or tantalum nitride, is deposited on the second insulating layer
5
and defines an interface
8
between the barrier layer
6
and the metal regions
4
.
A typical process flow for manufacturing the damascene structure
1
of
FIG. 1
may include depositing the first insulating layer
3
by any appropriate deposition process known in the art, forming the openings by lithography and etching, filling the openings
9
with a metal, such as copper, by, for example, electroplating, wherein prior to deposition of the copper a barrier layer (not shown) and a copper seed layer (not shown) may be deposited and the resulting structure is planarized by chemical mechanical polishing (CMP). Thereafter, the second insulating layer
5
, for example, silicon dioxide (SiO
2
), is deposited and patterned to form the vias
7
. Next, the barrier layer
6
is sputter deposited onto the second insulating surface
5
, wherein, as previously explained, voids (not shown) can be formed, especially at the interface
8
, i.e., between the underlying metal region
4
and the barrier layer
6
, caused by thermal stress due to heat created by the deposition of the barrier layer
6
and the subsequent cooling of the copper/barrier stack.
In general, interface voids are tiny compared to the via bottom area and are therefore difficult to be detected by electrical tests. In order to m

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