Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2000-07-13
2004-07-06
Auve, Glenn A. (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S305000, C710S058000, C713S401000, C713S500000, C713S501000, C327S119000, C375S376000
Reexamination Certificate
active
06760798
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present relation relates to an interface mechanism and particularly to an interface mechanism for interfacing a real-time clock operating at a first frequency with a data processing circuit operating at a second frequency.
2. Description of the Prior Art
Many data processing circuits utilise real-time clocks to provide a real-time clock value indicating, for example, the current day, date and time. Typically, when the data processing circuit is first activated, the correct day, date and time may need to be set. When the data processing circuit is shut down, power is maintained to the real-time clock, usually by a battery, so that the real-time clock may continue to operate. However, the real-time clock value may need to be updated for various reasons such as, for example, any cumulative inaccuracies of the real-time clock, a change of time zones or the loss of power to the real-time clock. Hence, it is known to provide an interface mechanism for interfacing the real-time clock with a data processing circuit which allows the real-time clock value to be updated.
The real-time clock will generally operate at a low frequency of typically 1 Hz and may therefore provide an incremented real-time clock value to the data processing circuit once every second. The data processing circuit will often be operating at a different frequency to the real-time clock, for example 30 MHz, and hence the interface mechanism will often need to handle signals received at different frequencies.
FIG. 1
describes such a known interface mechanism. The interface mechanism, generally
100
, interfaces a real-time clock, generally
110
, with a data processing circuit
190
. For clarity, signals issued in the data processing circuit frequency domain are annotated with the subscript f
2
, whilst signals issued in the real-time clock frequency domain are annotated with the subscript f
1
.
In overview, the data processing circuit
190
receives a real-time clock value C
f2
synchronised with the data processing circuit frequency and generated by the interface mechanism
100
in response to a real-time clock value C
f1
issued by the real-time clock
110
. The data processing circuit
190
may issue an update value W
f2
and a control signal CTL
f2
to the interface mechanism
100
to update the real-time clock
110
. The interface mechanism
100
then updates the real-time clock
110
and once the update is complete the real-time clock
110
issues an updated real-time clock value C
f1
.
The configuration of the real-time clock
110
will now be described in more detail. The real-time clock
110
comprises a multiplexer
160
, a register
170
an incrementer
180
and a clock generator (not shown) for generating a 1 Hz clock signal CLK
f1
. The real-time clock
110
is clocked by the 1 Hz clock signal CLK
f1
. The register
170
is coupled to the clock generator, the multiplexer
160
and the incrementer
180
. The register
170
stores the real-time clock value representing, for example, a time and date. The register
170
receives the clock signal CLK
f1
from the clock generator and the output from the multiplexer
160
. The output of the multiplexer
160
is loaded into, and output by, the register
170
each time the register
170
is clocked by the clock signal CLK
f1
(e.g. on the rising edge of the clock signal). The incrementer
180
receives the output of the register
170
, increments the value by one and outputs the incremented value to the multiplexer
160
. When the register
170
is next clocked, the incremented value will be loaded from the multiplexer
160
into the register
170
and output to the incrementer
180
.
The multiplexer
160
allows the real-time clock value to be incremented or updated. The multiplexer
160
receives the output of the incrementer
180
at one input and the output from the interface mechanism
100
at the other input. The multiplexer
160
is controlled by a signal LOAD received from the interface mechanism
100
. When the signal LOAD is asserted the multiplexer
160
outputs the value received from the interface mechanism
100
, whilst when the signal LOAD is not asserted the multiplexer
160
outputs the value received from the incrementer
180
. Hence, in the absence of the signal LOAD, the value in the register
170
is incremented every second and output as the real-time clock value C
f1
. When the signal LOAD is asserted, the update value W from the interface mechanism
100
is loaded into the register
170
when clocked by the clock signal CLK
f1
and output as the updated the real-time clock value C
f1
.
The configuration of the interface mechanism
100
will now be described in more detail. The interface mechanism
100
comprises a state machine
120
, a register
130
and a register
140
. The interface mechanism
100
is clocked by a clock signal CLK
f2
. The state machine
120
is coupled to the data processing circuit
190
, the real-time clock
110
, the register
130
and the register
140
. The state machine
120
controls the register
130
, the register
140
and the multiplexer
160
.
The state machine
120
receives the clock signal CLK
f2
and a control signal CTL
f2
from the data processing circuit
190
. The state machine
120
monitors the clock signal CLK
f1
issued by the clock generator of the real-time clock
110
. The state machine
120
will assert a signal LOAD
1
to the register
130
and a signal LOAD
2
to the register
140
in response to the control signal CTL,
f2
indicating that an update should take place. The register
130
is coupled to the data processing circuit
190
, the state machine
120
and the register
140
. The register
130
receives the update value W
f2
from the data processing circuit
190
.
When the signal LOAD
1
is asserted the update value W
f2
will be loaded into. and output by, the register
130
. The contents of register
130
are output to the register
140
. The register
140
is coupled to the register
130
, the state machine
120
and multiplexer
160
of the real-time clock
100
. The register
140
receives the update value W from the register
130
. When the signal LOAD
2
is asserted the update value W will be loaded into, and output by, the register
140
. The contents of register
140
are output to the multiplexer
160
.
Sync logic
150
is coupled to the output of the register
170
and to the data processing circuit. Sync logic receives the real-time clock value C
f1
output from the register
170
at the frequency f
1
and transforms this to a real-time clock value C
f2
having the same value but synchronised with the frequency f
2
.
The operation of the interface mechanism
100
and real-time clock illustrated in
FIG. 1
will now be described in more detail with reference also to FIG.
2
.
During normal operation of the real-time clock
110
, the register
170
may be activated with a value representing a time, day and date which is output as the real-time clock value C
f1
. The real-time clock value C
f1
n is transformed by the sync logic
150
and output as a real-time clock value C
f2
which is received by the data processing circuit
190
. As mentioned earlier, the real-time clock value C
f1
, is incremented every second when the register
170
is clocked by the clock signal CLK
f1
.
The real-time clock value C
f1
may be updated by the interface mechanism
100
in response to signals issued by the data processing circuit
190
.
In order to initiate the update of the real-time clock
110
, a control signal CTL
f2
and an update value W
2
are issued by the data processing circuit
190
to the state machine
120
shortly after a rising edge of the clock signal CLK
f2
. In response, the state machine
120
issues a signal LOAD
1
to the register
130
. The register
130
will then load and output the update value W
f2
when clocked by the next clock signal CLK
f2
.
The state machine
120
will then determine the state of the signal LOAD. If the signal LOAD is asserted then this indicates that a previous update of the real
Arm Limited
Auve Glenn A.
Lee Christopher E.
Nixon & Vanderhye P.C.
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