Interface latch for data level transfer

Details Interface latch for data level transfer Interface latch for data level transfer

2001-08-29

2003-02-18

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S063000, C326S014000

Reexamination Certificate

active

06522168

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed toward an interface latch for translating data from a first to a second supply voltage level, and more particularly to an transfer buffer interface latch having input and output terminals, and supplied with a first and a second voltage supply.
2. Description of the Related Art
In some integrated devices used in the audio radio field, it is very important to reduce the energy concentrated in a particular range of frequencies that could be propagated and could disturb other electronic applications. Even the clock switching in certain digital circuits could accumulate energy around the fundamental and harmonic frequency, which would result in decreased performance of the radio.
One solution to reduce this undesired effect is to reduce the power supply voltage in areas where the switching activity is higher. When using circuits with different power supplies, interfaces are useful to transmit data from circuits having a low voltage supply to circuits having a high voltage supply.
Generally, these interfaces use transfer level buffers able to convert logic states from low voltage to high voltage and vice-versa.
In some electronic devices the power supplies may not be constant, in that the specifications of the device may require that some power supplies are cleared during the work cycle. A difficult problem exists therefore in transferring data from a digital circuit having a low power supply to a digital circuit having a high power supply when the duty cycle of the low power supply is exceedingly short.
A general block diagram showing the process for switching logic levels between two supply voltages is seen in
FIG. 1. A
system
10
for switching includes a set of low-voltage logic
12
coupled to and providing an input to a transfer level buffer
14
. The output of the transfer level buffer
14
is supplied to a high-voltage logic
16
.
A more specific diagram showing an example of a transfer level buffer is shown in FIG.
2
. This well-known transfer level buffer interface
20
for shifting data levels between two different supply voltages is used to convert data signals that have a low voltage supply to data signals that have a high voltage supply. The data signals for the high voltage supply is sometimes referred to as the voltage supply of the load. The data input to the transfer level buffer
20
will either be LOW (0 volts) or HIGH-3V (3 volts), while the output with either be LOW (0 volts) or HIGH-5V (5 volts). In this way, the data level of input circuitry having a 3 volt power supply is changed to the data level of the load circuitry having a 5 volt power supply.
In
FIG. 2
, a high supply
22
is a higher voltage supply than a low supply
24
. A ground reference
26
is typically referenced at 0 volts. An input
30
accepts a data signal from the low supply circuitry, and an output
32
provides a data signal to the high supply circuitry.
The high supply
22
directly supplies two transistors, M
5
and M
6
, which are coupled in turn to M
4
and M
7
, respectively. Transistors M
4
, M
5
, M
6
and M
7
are all PMOS transistors. An NMOS transistor M
2
is coupled between the transistor M
7
and the ground
26
. An input signal from the input
30
is connected directly to the gates of M
7
and M
2
. Another NMOS transistor M
0
is coupled between M
4
and the ground
26
. The output terminal
32
is placed between the transistors M
4
and M
0
.
The low supply
24
supplies a PMOS transistor M
3
, which is coupled to an NMOS transistor M
1
, which is in turn coupled to the ground
26
. The gates of the transistors M
1
and M
3
are linked together and to the input
30
. The combination of M
1
and M
3
makes an inverter, with the inverter input being the signal on input
30
, and the inverter output being the connection between the transistors M
1
and M
3
. This inverter output is coupled to and drives the gates of M
0
and M
4
.
The operation of the transfer level buffer
20
of
FIG. 2
will now be discussed. When the signal on the input
30
is LOW, the gates of transistors M
1
, M
2
, M
3
, M
6
and M
7
are supplied with 0 volts. The gates of transistors M
0
and M
4
are set to voltage of the low supply
24
(Low supply voltage, or LSV) because the transistor M
3
is ON, while the transistor M
1
is off. M
5
is set to the voltage of the high supply
22
(High supply voltage or HSV). Because of this biasing, M
6
and M
7
, are both ON, and cause the transistor M
5
to switch OFF. Because M
0
is driven with the LSV, M
0
is ON and ensures that the signal at the output
32
will be LOW. Therefore, when the signal on the input
30
is LOW, the signal on the output
32
of the transfer level buffer
20
is also LOW.
Conversely, when the signal on the input
30
is HIGH-LSV, which means it is at the voltage of the low supply
24
, the gates of the gates of M
1
, M
2
, M
3
and M
7
are also driven with the LSV. The gates of M
0
, M
4
, and M
5
are supplied with a LOW signal, while M
6
is driven with the HSV. Because of this biasing, M
4
and M
5
, are both ON, and M
0
is OFF, which causes the output
32
to rise to HIGH-HSV, the level of the high supply
22
. Thus, when the signal on the input
30
is HIGH-LSV, the signal on the output
32
of the transfer level buffer
20
is HIGH-HSV.
In this way, the transfer level buffer
20
provides at its output
32
voltage signals of 0 volts or 5 volts (or whatever the high supply
22
voltage is), while its input
30
accepts inputs of 0 volts or 3 volts (or whatever the low supply
24
voltage is).
One major problem with the transfer level buffer
20
is that it is unable to provide the proper signals at its output
32
if the low power supply
24
is removed. For instance, if the low supply
24
shut off because the electronic device that includes the transfer level buffer
20
required a short duty cycle of the low supply, there is no way to produce the necessary LOW and HIGH-HSV signals on the output
32
of the interface
20
.
The underlying technical problem of this invention is to maintain an output at the transfer level buffer even when the low voltage supply switches off, thereby overcoming the limitations of prior art solutions for transfer level buffers.
BRIEF SUMMARY OF THE INVENTION
The disclosed embodiment of the present invention provides a particular latch architecture in the transfer level buffer, and an additional circuit portion that is operative when it receives a signal that indicates the low voltage supply has shut down.
In accordance with one embodiment of the invention, an interface for translating data of different voltages is provided. The interface includes an input terminal structured to accept an input from a circuit at a first voltage level; an output terminal structured to provide an output from the interface; a first circuit portion powered by a power supply generating the first voltage level; a second circuit portion powered by a power supply generating a second voltage level that is higher than the first voltage level; and a power supply detection circuit structured to accept a detection signal, the detection circuit coupled to the first and second circuit portions and further structured to maintain a correct output at the output terminal after the power supply generating the first voltage level no longer supplies the first voltage level.
In accordance with another embodiment of the invention, a method of translating data having a first data level to a second data level is provided. The method includes powering a first portion of a circuit with a power supply generating a first voltage operating level; powering a second portion of the circuit with a power supply generating a second voltage operating level; providing an input signal on an input terminal; generating an output at the second voltage operating level on an output terminal responsive to the input signal; and latching data from the input signal prior to interruption of the power supply having the first voltage operating levels to maintain the

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