Interface having a bus master arbitrator for arbitrating occupat

Details Interface having a bus master arbitrator for arbitrating occupat Interface having a bus master arbitrator for arbitrating occupat

1995-04-06

1997-10-07

Harvey, Jack B.

395726, G06F 1500

Patent

active

056757506

ABSTRACT:
An interface for a high-performance graphics adapter is provided. In a computer system which includes a host processor, a coprocessor in the form of a graphics system processor, and memory addressable by both the host and coprocessors. An application computer program running on the host processor utilizes a graphics operating system, such as an Extended Graphics Array Input/Output System (XGA BIOS) to write graphics data in XGA format to the memory. A controller translates memory addresses generated by the XGA BIOS (and hence the host processor) into memory addresses recognized by the coprocessor. One or more graphics controllers selectively swap pixel data between Intel order and Motorola order and store the graphics data, into an XGA video-random-access memory (RAM) buffer. A back-end gate array parallel-serial converts input display data in units of designated pixel data, and the graphics data is displayed on a CRT.

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inmos, "XGA Software Programmer's Guide", First Edition 1991, 72OEK 258 00 (Sep. 1991).
Texas Instruments, "TMS34020, TMS34020A, Graphics System Processors", SPVS004B (Mar.1991-Revised Oct. 1990).
Texas Instruments, "TMS34020 User's Guide", 2564006-9721 revision (Aug. 1990).

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