Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2001-06-04
2004-08-10
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S311000
Reexamination Certificate
active
06775733
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an interface that is used for Universal Serial Bus (USB) communications, and more particularly, to a universal media interface for use between a USB host controller and a root hub.
2. Background Art
USB is commonly used to interface data communications or connections between a personal computer (PC) and peripheral devices (such as printers and scanners, among others).
FIGS. 1 and 2
are schematic diagrams illustrating the typical USB connection between a host system and one or more peripheral devices.
Referring first to
FIG. 1
, the host system
10
(if embodied in the form of a PC) would typically include a motherboard
12
. A CPU
14
, a BIOS
16
, a memory
18
(such as a DRAM), and a core logic
20
can all be provided on the motherboard
12
in manners that are well-known in the art. At least a first port
22
can be positioned adjacent a rear end panel of the host system
10
and at least a second port
24
can be positioned adjacent a front end panel of the host system
10
.
FIG. 2
illustrates the interface of the core logic
20
with the peripheral devices. Specifically, the core logic
20
has a south bridge
26
that is coupled to a PCI bus
28
for communicating data inside the host system
10
. The south bridge
26
includes a USB host controller
30
, and a root hub
32
communicating with the controller
30
and one or more analog physical layers (PHY)
34
. As is well-known in the art, a physical layer is the lowest (signal) level of communication technology. The PHYs
34
provide low level analog differential signals to USB devices
36
(such as peripherals) via lines A and B. The data transfer rate can vary depending on the applicable USB standard. For example, for USB 2.0, the data transfer rate is 480 MHz (high speed), and for USB 1.1, the data transfer rate is 12 MHz (full speed) or 1.5 MHz (low speed).
Unfortunately, when the circuits illustrated in
FIGS. 1 and 2
are used for USB 2.0, the high speed data transfer rate of 480 MHz may result in certain undesirable problems. First, the yield on the PHYs
34
may be lowered, thereby lowering the yields on the south bridge
26
which will increase the costs of production. The low yield may be attributable to the low limitation to process parameter deviation, and low immunity to the coupling noise of the high speed analog circuit. Second, the signal integrity on the USB port(s)
24
adjacent the front end panel will be compromised. As shown in
FIG. 1
, the south bridge
26
of the core logic
20
is typically closer to the rear end of the motherboard
12
so that the line A from port
22
is short. However, the length of the line B from port
24
is usually much longer. As a result, the long line will distort the high speed analog signals that are being transmitted along line B, thereby damaging the integrity of the signal (i.e., the signals may not be consistent). Third, the high clock rate along line B (i.e., 480 MHz) may cause high electromagnetic interference (EMI) at the motherboard
12
because high speed USB signals traveling along the long line B will emit electromagnetic waves through the line B, which causes high EMI. This high EMI will increase the costs of achieving electromagnetic compatibility.
To overcome the above-mentioned problems, it has been suggested to separate the PHYs
34
from the south bridge
26
, and to provide the PHYs
34
in the form of a separate chip SC, as illustrated in FIG.
3
. Unfortunately, such an approach raises other difficult problems. For example, such an approach will require an interface between the PHYs
34
and the root hub
32
. This interface may require an excessive number of pins at the south bridge
26
. For example, if you have six ports, and each port uses 15 pins (under the currently known Intel UTMI standard), this will result in a total of 90 pins. This excessive number of pins will significantly increase the cost of the core logic
20
.
Thus, there still remains a need for an interface for use between a USB host system and a peripheral device which overcomes the above-mentioned problems.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a USB interface between a host system and a peripheral device which does not compromise the integrity of the transmitted signals.
It is another object of the present invention to provide a high speed USB interface between a host system and a peripheral device which does not have a negative impact on the yield of the core logic.
It is yet another object of the present invention to provide a high speed USB interface between a host system and a peripheral device which minimizes EMI.
It is yet another object of the present invention to provide a high speed USB interface between a host system and a peripheral device which not require an excessive number of pins.
To accomplish the objectives of the present invention, there is provided a USB host system that includes a core logic having a host controller and a first root hub coupled thereto, a second root hub external to the core logic and coupled to the first root hub via a mapping interface, and a plurality of USB ports coupled to the second root hub, each of the USB ports adapted to couple an external USB device.
REFERENCES:
patent: 5890015 (1999-03-01), Garney et al.
patent: 6205501 (2001-03-01), Brief et al.
patent: 6535947 (2003-03-01), Amoni et al.
patent: 6542946 (2003-04-01), Wooten
patent: 6567875 (2003-05-01), Williams et al.
patent: 6587053 (2003-07-01), Lee
patent: 2002/0116565 (2002-08-01), Wang et al.
Chang Liang-Hsi
Chu Ping-Ying
Kao Chao-Ting
Rong Iun-Bohr
Auve Glenn A.
Sun Raymond
Winbond Electronics Corp.
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