Interface for logic simulation using parallel bus for concurrent

Details Interface for logic simulation using parallel bus for concurrent Interface for logic simulation using parallel bus for concurrent

1996-04-03

1998-02-24

Lee, Thomas C.

Boots, shoes, and leggings

395500, 3642292, 3642397, G06F 300

Patent

active

057219532

ABSTRACT:
A host interface for a logic simulation machine for transferring data between the logic simulation machine and a host computer is disclosed. The host interface includes a First-In First-Out buffer provided between the logic simulation machine and the host computer for temporarily storing data being transferred between the logic simulation machine and the host computer until a receiver of the data is ready to receive the data. The host interface minimizes delays due to host interaction with the logic simulation machine during the communication between the host and the logic simulation machine.

REFERENCES:
patent: 4306286 (1981-12-01), Cocke et al.
patent: 4724520 (1988-02-01), Athanas et al.
patent: 5548785 (1996-08-01), Fogg, Jr. et al.
Arnold et al., "A hierarchical, restructurable multi-microprocessor architecture", 1976, pp. 40-45, Publisher: IEEE, New York, NY, USA.

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