Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1998-12-08
2001-08-07
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S003100, C345S094000, C345S099000, C345S100000, C345S103000, C345S087000, C345S205000, C345S213000
Reexamination Certificate
active
06271821
ABSTRACT:
CLAIM OF PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C § 119 from an application entitled Interface For Liquid Crystal Display earlier filed in the Korean Industrial Property Office on Dec. 8, 1997, and there duly assigned Serial No. 97-66792 by that Office.
FIELD OF THE INVENTION
The present invention concerns a video interface for communicating video data to an LCD (liquid crystal display) apparatus used in a computer, television, etc.
BACKGROUND OF THE INVENTION
In order to enhance the resolution of an LCD such as the thin film transistor type, i.e., TFT-LCD, it is required to increase the frequency of the data clock signal used in the drive IC for the LCD. However, this is limited by the charging characteristics of the LCD and the drive IC. Alternatively, there has been proposed other systems to enhance the resolution without increasing the frequency of the data clock, which includes a n-pixel/1-clock pulse system for driving n pixels per 1 clock pulse and a dual scan system for scanning the screen simultaneously with two lines. Meanwhile, it is also required to make the frame memory have the responsive speed of at least 160 MHz and the storage capacity of 3.9 Mytes to obtain the display resolution of SXGA (super extended graphics array) order, for example, 1280×1024. Nevertheless, the responsive speed of the conventional frame memory is limited to 50 MHz.
Referring to
FIG. 1
, there are shown a plurality of frame memory blocks and multiplexers constituting a conventional interface for communicating R (Red) video data to the TFT-LCD of the dual scan system. In operation, the input video signal is firstly stored into the frame memories
11
to
18
, and then divided into an upper side image part and a lower side image part applied to the TFTLCD (not shown). During this application, it is necessary to consider the responsive speed of the drive IC (integrated circuit) of the LCD and the gate pulse duration required for sufficiently charging the liquid crystals. In this case, the conventional interface requires 24 frame memories to process a least number of video data by dividing the frequency of the video signal by four and dual scanning according to Equation 1, as follows:
24=4 (frequency dividing)×2(Dual Scan)×3(RGB 3 Colors) (1)
In this case, each frame memory requires the storage capacity of 167 KBytes. Since the memories commercially available have the storage capacities of 130, 260, 330 or 520 KBytes, the memory with the storage capacity of 260 KBytes may be used as the frame memory. Hence, if the 24 frame memories each having 260 KBytes are used to constitute the total storage capacity to process the video data, there occurs a memory loss of 2.4 MBytes which is the difference between the required storage capacity 3.9 MBytes and the total storage capacity 6.3 MBytes.
Other known systems to drive a dual scan LCD, incorporated herein by reference, are exemplified by U.S. Pat. No. 5,387,923 to Phillip E. Mattison, et al. entitled VGA Controller UsingAddress Translation To Drive A Dual Scan LCD Panel And Method Therefor; U.S. Pat. No. 5,537,128 to David Keene, et al. entitled Shared Memory For Split-Panel LCD Display Systems; and U.S. Pat. No. 5,617,113 to Dennis W. Prince entitled Memory Configuration For Display Information.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an LCD interface for communicating the video signal to the LCD, which may optimize the storage capacity, divide the frequency of the video signal by four and generate 2 pixels per a single clock pulse in the dual scan system.
According to an embodiment of the present invention, an LCD interface for communicating a video signal to an LCD comprises a video input device for separating the video signal into a synchronizing signal and R (Red), G (Green) and B (Blue) video signals having a resolution of m rows by n columns, a controller for generating a first clock frequency, a second clock frequency and a third clock frequency being half the second clock frequency based on the synchronizing signal, a R signal converter for dividing the frequency of the R video signal by four according to the first clock frequency to sequentially generate two adjacent pixel column data simultaneously starting both from the first pixel row and the ((m/2)+1)
st
pixel row respectively to the (m/2)
th
pixel row and m pixel row according to the second clock frequency fo so that the four pixel data arranged in the adjacent pixel columns are simultaneously generated, a G signal converter for dividing the frequency of the G video signal by four according to the first clock frequency to sequentially generate two adjacent pixel column data simultaneously starting both from the first pixel row and the ((m/2)+1)
st
pixel row respectively to the (m/2)
th
pixel row and m
th
pixel row according to the second clock frequency fo so that the four pixel data arranged in the adjacent pixel columns are simultaneously generated, a B signal converter for dividing the frequency of the B video signal by four according to the first clock frequency to sequentially generate two adjacent pixel column data simultaneously starting both from the first pixel row and the ((m/2)+1)
st
pixel row respectively to the (m/2)
th
pixel row and m
th
pixel row according to the second clock frequency fo so that the four pixel data arranged in the adjacent pixel columns are simultaneously generated, and an LCD driver for supplying the pixel data from the R G, B converters to an LCD panel.
Preferably, each of the R, G, B converters comprises a first frame memory having a matrix of data storage cells arranged in j rows (m/4)×k columns (n) to store the first group of pixels obtained by dividing by four the m×n pixel data from the video input device, a second frame memory having a matrix of data storage cells arranged in j rows (m/4)×k columns (n) to store the second group of pixels obtained by dividing by four the m×n pixel data from the video input device, a third frame memory having a matrix of data storage cells arranged in j rows (m/4)×k columns (n) to store the third group of pixels obtained by dividing by four the m×n pixel data from the video input device, a fourth frame memory having a matrix of data storage cells arranged in j rows (m/4)×k columns (n) to store the fourth group of pixels obtained by dividing by four the m×n pixel data from the video input device, a first line memory for storing the line data of the odd-numbered pixel data rows of the first frame memory according to the second clock frequency and for outputting the stored pixel data according to the third clock frequency, a second line memory for storing the line data of the odd-numbered pixel data rows of the first frame memory according to the second clock frequency and for outputting the stored pixel data according to the third clock frequency, a third line memory for storing the line data of the odd-numbered pixel data rows of the third frame memory according to the second clock frequency and for outputting the stored pixel data according to the third clock frequency, a fourth line memory for storing the line data of the odd-numbered pixel data rows of the fourth frame memory according to the second clock frequency and for outputting the stored pixel data according to the third clock frequency, a first multiplexer for selectively receiving the pixel data output from the first or third line memory and outputting the pixel data of the first or third line memory according to the second clock frequency, a second multiplexer for selectively receiving the pixel data output from the second or fourth line memory and outputting the pixel data of the second or fourth line memory according to the second clock frequency, a third multiplexer for selectively receiving the pixel data of the even-numbered data rows output from the first or third frame memory and outputting the pixel data of the even-
Chung Seong-eun
Sung Jun-Ho
Bushnell , Esq. Robert E.
Hjerpe Richard
Samsung Electronics Co,. Ltd.
Zamani Ali
LandOfFree
Interface for liquid crystal display does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interface for liquid crystal display, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interface for liquid crystal display will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2511806