Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1996-12-26
2001-08-21
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C710S010000, C711S171000, C711S172000
Reexamination Certificate
active
06279069
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to flash electrically-erasable programmable read only memory (“EEPROM”) and, more particularly, to methods and an apparatus for providing an interface for flash EEPROM memory arrays that allows determination of the characteristics of the memory array.
BACKGROUND OF THE INVENTION
Flash EEPROM memory arrays are being used for many purposes in present day digital systems (e.g., computers) because of the ability of flash EEPROM memory arrays to retain data when power is removed and to be easily reprogrammed without being removed from a system. A flash EEPROM memory array is comprised of floating gate field effect transistor devices arranged in row and column fashion. The charge stored on the floating gate of such a memory transistor may be changed by programming, and the state of the charge may be detected by sensing voltage across the device. Because these flash EEPROM arrays may be easily reprogrammed, they are being used as substitutes for normal EPROM arrays to provide read-only memory that may be easily updated.
A flash memory array is accessed for reading and writing in the same manner as are dynamic random access memory (DRAM) arrays using row and column addressing in byte, word, or larger sequences of bits. However, because of the manner in which data are stored, a flash memory array, unlike a typical DRAM device, cannot be overwritten without first erasing the memory cells. Flash memory arrays used as substitutes for EPROM arrays are typically erased in large blocks (that may constitute the entire array) before being reprogrammed.
Flash EEPROM memory arrays are also being used to provide smaller lighter functional equivalents of electromechanical hard disk drives. Flash memory arrays designed to replace hard disk drives (referred to herein as “flash disk drives”) operate more reliably and are not as sensitive to physical damage as electromechanical hard disk drives. Because of these characteristics, flash disk drives are especially useful in portable computers where space is at a premium and weight is important.
Electro-mechanical disk drives have historically used an industry standard interface referred to as an “ATA interface.” The ATA interface was specifically designed to provide communication between a computer system and a rotating electromechanical disk drive. Because of this, the ATA interface was defined in terms of primitive functions that are directly applicable to directly-overwritable, block read/write, rotating media. Such primitive functions include “do a slow seek for a logical address or a cylinder head sector,” “read a sector or multiple sectors,” and “write a sector.”
On the other hand, exemplary flash EEPROM array primitive functions include “read and write at the byte, word, or small block level” and “erase at a large block level.” The ATA interface does not communicate in flash memory array primitives. When a flash disk drive replaces an electromechanical disk drive, it uses the ATA interface to communicate with other computer components. Therefore, it has been necessary to provide circuitry by which the signals used by a computer to access electromechanical hard disk drives may be understood by the flash disk drive. The process of translating electromechanical rotating disk drive functions to flash disk drive functions has required a substantial amount of hardware and software.
For example, one type of flash disk drive interposes a command user interface on the same silicon substrate (chip) with the flash memory array to interpret the commands provided at the ATA interface. The flash disk drive command user interface accepts the ATA signals and controls the operations necessary to access the flash disk drive. The flash disk drive command user interface typically includes state machines that receive commands intended for a rotating disk, decode those commands, and generate commands adapted to carry out the purposes of the ATA commands within a flash disk drive.
Recently, there has appeared a lower cost alternative to a flash disk drive that combines disk emulation software running on a host computer with a low cost flash memory device array. The flash memory device array comprises one or more flash memory devices contained in one of several system packaging options, including a removable memory card, a system-resident single-in-line-memory module (SIMM), and a resident flash array (devices mounted directly on the system motherboard). The combination of any one of these plain flash memory device subsystems with disk emulation software is referred to in this specification as a flash disk emulator.
Many of the operations necessary for either a command user interface or a flash disk emulator to translate from commands phrased in primitives of a rotating disk are quite complicated. For example, in some flash disk drives and other flash memory devices data are first written to empty blocks of the memory array chosen under control of the command user interface; and then the physical address at which the data are stored is recorded in lookup tables along with the rotating disk addresses provided externally. This allows the data to be recovered when the rotating addresses are provided.
Early flash memory arrays addressed data in single bytes. As flash memory arrays have evolved, addressing in words and double words have become possible, often in the same array. The ability to provide these different forms of addressing have complicated the operations of the device command user interface. Recently, flash memory arrays have been devised that use buffering to allow the transfer of large amounts of data even though the array cannot immediately handle that data because of its slower combined erasing and writing speed. These enhancements increase the complexity of flash disk drive and flash emulator operations.
The basic requirement that flash memory be erased in large blocks further complicates operations that flash disk drives and flash disk emulators must carry out. When data are updated, stale data that cannot be overwritten must be marked invalid, the new data must be written to empty array space, and the address tables must be updated to provide a new physical address. This method of updating causes the data in a file to be written to discontiguous positions. When a sufficient amount of data in a large block becomes invalid, the remaining valid data must be copied to empty array space in some other block, the address tables must be updated, and the block must be erased to recover the array space. In prior art devices, this has required means for determining the status of individual blocks and cells of each device at all times.
The writing of flash EEPROM devices is slower than writing DRAM memory because storing data on the floating gate of a transistor requires substantial voltages and relatively long charging times. Both the writing process and the copy process are thus too long to be competitive with DRAM write times. A write state machine is typically positioned on the chip to assist a device command user interface and is used to conduct write and copy operations so that data are accurately stored without overwriting other data in the array. Moreover, the erase process (a process not required by DRAM or electromechanical memory) is typically slow, as long as one-half second for some flash drives. Because of this, the erase process is typically conducted as a background process run by the write state machine or by additional on-chip state machines under control of the flash disk drive firmware or flash disk emulator software operating beneath their respective command user interfaces. Substantial resources have been required to keep track of block status in order to accomplish these operations. The time required to conduct erase operations is such that some flash memory device command user interfaces accepts commands that suspend the erase operation to allow various other operations to occur.
Recently, flash memory arrays have been devised that allow the storage of more than one bit of data in a single memory c
Christopherson Mark
Kendall Terry
Robinson Kurt B.
Bataille Pierre-Michel
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Kim Matthew
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