Interface for establishing operability between a processor...

Details Interface for establishing operability between a processor... Interface for establishing operability between a processor...

2011-04-26

2011-04-26

Rinehart, Mark (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

System configuring

C710S311000, C710S313000, C710S314000, C710S316000

Reexamination Certificate

active

07934032

ABSTRACT:
Described are electronics systems and methods for distributing a limited number of lanes of a PCI Express-based processor (CPU) module among a plurality of PCI Express-based I/O modules with which the CPU module is in communication. The CPU module receives a code from each I/O module over a sideband interface between that I/O module and the CPU module. The coded signal represents a link-width capability of the I/O module. The CPU module is configured to allocate a link width to each I/O module based on the fixed number of lanes and the link-width capability as represented by the coded signal received from that I/O module. The link between CPU module and each I/O module is trained in accordance with the link width allocated to that I/O module.

REFERENCES:
patent: 7099969 (2006-08-01), McAfee et al.
patent: 7325086 (2008-01-01), Kong et al.
patent: 2009/0006708 (2009-01-01), Lim

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