Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Patent
1997-10-15
1999-09-21
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
G06F 1200
Patent
active
059567414
ABSTRACT:
A configurable RAM interface connecting a bus to RAM is adapted to receiving large multiword variable length tokens at a high data arrival rate, using a swing buffer and a buffer manager. An address source provides complete addresses to the interface. The buffer manager has a state machine which transitions among a plurality of states, maintaining status information about the buffers, allocating the buffers for reference by a write address generator, clearing the buffers for occupation by subsequently arriving data, and maintaining status information concerning the buffers. The buffer manager also examines tokens of received data in order to update the status of the arrival buffer.
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Bollella Donald
Braun Robert T.
Chan Eddie P.
Discovision Associates
Gaetje Clay E.
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