Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-10-27
2001-11-20
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06321369
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to methods and apparatuses used in creating and refining electronic designs, and more particularly to methods and apparatuses for use in design environments which support multiple variations of structural and/or functional entities within a design project.
Integrated circuits and in particular programmable logic circuits, such as programmable logic arrays and programmable gate arrays, are well known and can be designed for use in a variety of devices. These integrated circuits are typically designed with one or more software tools, such as design automation tools. By way of example, the MAX+PLUS® II development system available from the Altera Corporation of San Jose, Calif., provides a single integrated environment that offers such features as schematic, text and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device configuration.
The technical documentation available for the MAX+PLUS® II development system, such as “MAX+PLUS® II Programmable Logic Development System: Getting Started” (Version 6.0 Serial No. P25-04803-02) and the “MAX+PLUS® II Programmable Logic Development System AHDL” manual (e.g., Version 3.0, Serial Number P25-04804-00) are hereby incorporated for all purposes in their entirety, as are U.S. Pat. Nos. 4,609,986; 4,617,479; 4,677,792; 4,774,421; 4,831,573; 4,864,161; 4,871,930; 4,899,067; 4,899,070; 4,903,223; 4,912,342; 4,930,107; 4,969,121; 5,045,772; 5,066,873; 5,091,661; 5,097,208; 5,111,423; 5,128,565; 5,138,576; 5,144,167; and 5,162,680 which are mentioned therein.
Design tools, such as those provided in MAX+PLUS® II, may define an electronic design as a tree having multiple levels of entities that are arranged in a hierarchy. For example, a high level block might specify a processor having certain functionality. A low level entity might specify specific processing circuitry such as AND gates, accumulators, flip flops, multiplexers, etc. within the processor. By supporting multiple levels of entities within the design, these design tools allow for different levels of design abstraction. These different levels of abstraction typically allow designers to focus on custom structures and/or functions, reuse previously designed functions or design blocks, and/or build large and more complex megafunctions (i.e., off the shelf design blocks such as processors, DSP functions, bus controllers and interfaces) for later use. Thus, design tools such as these which present hierarchical designs and facilitate use of off the shelf entities can reduce the development time and lower the design costs.
As is well known, circuit designers typically use design tools to adjust or “tweak” particular entities to produce a specific result. For example, assume that a specific design block contains within it a logic block, such as an adder or multiplexer. The designer will typically specify that a multiplexer logic function, for example, is to be performed with a specific number of input signals, and that the output of the multiplexer logic function is to be provided to a specific circuit and/or pin. In defining the attributes of the multiplexer logic function, in this example, the designer may specify specific timing, sizing, location, and/or power requirements, or other like requirements that the resulting multiplexer circuit would be required to meet. These user specified attributes are commonly referred to as assignments or parameters.
For example, assume that the multiplexer logic function has a collection of logic option assignments known as “style” which can be set by the designer to define that the resulting multiplexer has a general behavior. Thus, for example, the designer may set “style” equal to “standard” (better fit) or to “fast” (better performance) depending upon the desired optimization. The design tool will then use the style attribute to select, for example, the proper components (e.g., logic elements of a programmable logic device) and/or location necessary to meet the timing requirements specified in the style attribute. Those skilled in the art will recognize that other styles, assignments, and/or parameters can be set or established in a similar fashion.
In conventional design tools, the attributes for an entity (e.g., identified function, circuit, component, and/or design block) are usually specified within an assignment file that is read during compilation stages. Various techniques are available for making an assignment to a particular entity. A “relative hierarchical assignments” technique will be described below.
Frequently, users want to compare related but distinct designs for achieving different goals, such as increasing device speed or fitting circuitry on a given chip or floorplan. Such different objectives could be supported by different assignments made globally or specifically within a bas e design. For designers seeking to compare the results of such different designs, such as for example designs having different assignments, the current generation of design tools require that several designs be created (e.g., each having differing assignments), stored, and compiled separately. This duplication of effort tends to be tedious, time consuming and can place a strain on processing and related computational resources.
In an effort to reduce the time required to create, compile, and simulate a variation of an existing design, some designers have been forced to create elaborate programs, such as Unix® shell scripts and the like, that parse through the design data files and change certain parameters. Those designers who do not have the ability, resources or time to create and test such programs are left to copying the design files and modifying the various parameters manually or through the design tool's interface. Such programs and/or manual manipulation techniques generally limit the user's efficiency. Moreover, these programs and/or manual techniques often output multiple versions of the associated design data files. These files must be identified as being associated with the correct design variation. In large designs and designs having many variations, the resulting number and overall size of the associated data files can be difficult to manage, thereby limiting the designer's efforts.
With this in mind,
FIG. 1
is a flow-chart that illustrates a conventional design method
10
that might be used to vary the design of a circuit created with a design tool. Method
10
begins with the user creating an initial or first design with the tool in a step
12
. The result of step
12
is that a first design is embodied in one or more associated data files
13
, including for example first design data and first assignment data. In a step
14
the first design is typically compiled by way of the design tool. The results of the compile can then be recorded, as in a step
16
.
Assuming that the designer wishes to create a variation of the first design, the designer can, for example, generate or create a program or script file in a step
18
. Such programs or scripts are typically not supported by the design tool and as such the designer will usually require additional resources. In a step
20
the designer modifies the associated data files of the first design. This can, for example, include making a copy of the associated data files, renaming the files, etc., so as to not effect the actual first design.
Once a copy of the data files has been made, then the designer can manually change parameters or assignments therein, or can run the program or script to make specific changes to the file. The result of step
20
is that one or more variation data files are created, such as “Nth Design” files
21
. In a step
22
, the variation data files are compiled and the results are then recorded in a step
24
. Notice that steps
20
-
24
can be repeated for any number of variations, and that each variation will result in another unique Nth design file.
For each variation a separate script or manual operation is requir
Heile Francis B.
Rawls Tamlyn V.
Altera Corporation
Beyer Weaver & Thomas LLP
Garbowski Leigh Marie
Smith Matthew
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