Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1999-03-30
2002-06-18
Bragdon, Reginald G. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S165000, C711S202000
Reexamination Certificate
active
06408366
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an interface device, a method and a monitoring system for providing status information about the status of a hardware device to a plurality of process means. The invention particularly addresses the problem how the status information about the current state of a hardware device can be simultaneously and independently provided to several process means which may each require an access to at least a part of said status information or to the complete status information.
BACKGROUND OF THE INVENTION
In many applications it is necessary to supervise the state of a hardware device. For example, if the hardware device is a machining apparatus, a control device (e.g. a control computer) needs to know whether the machining tool of the machining apparatus has responded correctly to a command issued by the control device. Therefore, the machining tool outputs a status information to the control device which indicates the current status of the machining tool, i.e. whether it is currently executing a cutting operation, a drilling operation etc. Furthermore, the status information may indicate the positioning of the machining tool with respect to a workpiece.
Furthermore, in most microprocessor controlled hardware devices there is provided a status register into which the hardware device writes the current status information of the hardware device. This is for example of particular importance in multi-tasking systems where it is essential to have an exact knowledge about each task's current status such that another task is correctly timed.
There is no problem when a status memory is provided into which the status information is written and if there is only one process means (e.g. a computer) which once accesses this status information in the status memory and subsequently processes said status information. Whenever a new status information is written into the status memory the process means can read out the status information and perform the processing thereof, the aim being to detect when a change in the status information has occurred.
As will be explained below with further details, a non-latching or a latching status memory may be used. In a non-latched status memory the status information always exactly reflects the current status of the hardware device, i.e. the status information is not held in the memory up to the next polling timing where the memory is polled. By contrast, in a latching memory the status information is set according to the current status of the hardware device, however, it is held (i.e. latched) in the status memory up to the next polling timing (i.e. rending). After being polled the status information in the status memory is reset and is only set with the next change of the status of the hardware device.
Thus, the polling process means detects the change of a status (i.e. an operation state) of said hardware device even when the state of the hardware device has changed from a state B to state A and back to state A inbetween two polling cycles. This is shown in FIG.
4
. When a process mean reads the state before t
0
(1. polling cycle) and then at t
2
(next polling cycle) the process mean will read state B at both cycles in case of non-latched memory. So the temporary state-A (during t
0
to t
1
) will not be detected.
In case of latched memory the process mean will detect state A at time t
2
although the hardware state has already changed back to state B.
The usage of a non-latching memory results in the disadvantage that the process means can not detect the status change described before. As opposed to the usage of non-latching memories, the latched memory has the advantage that the status of the hardware device is at least kept in the memory until the first polling, since after a change of status the information is held in the memory. However, in this case the status information in the memory is reset when a polling is executed such that the information can only be read by one single process means.
The status information itself may be quite complex information and it may be necessary that several independent process means successively or simultaneously access said status information. If for example the status information relates to different operation states of the machining apparatus discussed above, then such status information may contain a first information relating to the “drilling state”, a second information relating to the “cutting state” and a third information relating to the “positioning state”. Since the machine tool might be controlled by several independent process means, for example one for the drilling operation and one for the cutting operation, a part of the entire status information relating to the “positioning state” must be accessible by the drilling process means as well as the cutting process means, sequentially or even simultaneously.
Most importantly, the individual independent process means may have different clock rates for access operation, such that accidentally two process means may access the same status information (or a part of it) such that a collision occurs. Furthermore, in case the status memory is based on a latching memory, the status information will be reset by one process means making it impossible for a second process means to read this information again, since it will be reset by the first process means.
Often the state information is set and reset as individual status or indication bits in the memory. They may be set/reset individually or as one word consisting of a number of indication bits at predetermined bit positions in the memory.
FIG. 3
shows the problems described above with more details when individual bits are used as status information in a memory. In
FIG. 3
there is shown a hardware device HW which includes an interface device ID through which status information about the status of the hardware device HW is communicated to a monitoring processing device SW which comprises several process means A, B, C. The interface device ID comprises a memory MEM
1
with a number m of registers REG
1
1
, . . . , REG
1
m
. Each register can hold k indication bits, indicated with a dot. The indications are thus assembled bit-wise in the memory registers. The registers may be latched or non-latched. The three process means A, B, C can access (e.g. via a software access) SAA, SAB, SAC each register of the memory MEM
1
to read out the indication bits for further processing. The registers can only be read entirely by the monitoring processing device SW, i.e. its respective process means A, B, C. Assuming k=4 in
FIG. 3
, this means that always all four bits of a register are read if a register is accessed and if it is a latching register all status information is reset. That is, the hardware device HW continuously writes bits into a register as a part of the complete status information, wherein all bits stored in all registers form the complete current status information about a current status of the hardware device HW. The bits can be independently written and may individually change at different times.
Although in
FIG. 3
the interface device ID is shown as being part of the hardware device HW, it may also be situated in the monitoring processing device SW or between the hardware device HW and the monitoring processing device SW. A monitoring system SYS is formed by the monitoring processing device SW and at least the interface device ID.
As indicated above, the indication registers REG
1
1
, . . . , REG
1
m
can be latched or non-latched, and
FIG. 4
shows a timing diagram for both cases. The top graph indicates the current state of the hardware device HW. At times t
0
, t
1
, t
3
a change of the current state of the hardware HW occurs, namely from a state B to a state A at time t
0
, from a state A to a state B at time t
1
and from a state B to a state A at time t
3
.
In the memory MEM
1
state A and state B will respectively be indicated by a particular combination of bits A, B in the individual registers REG
1
1
, . . . , REG
1
m
. As is indica
Lorenz Stefan
Wassew Alexander
Bragdon Reginald G.
Jenkens & Gilchrist P.C.
Telefonaktiebolaget LM Ericsson (publ)
LandOfFree
Interface device, method and monitoring system for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interface device, method and monitoring system for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interface device, method and monitoring system for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2970231