Interface device having variable data transfer mode and...

Details Interface device having variable data transfer mode and... Interface device having variable data transfer mode and...

2005-05-24

2005-05-24

Vo, Tim (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S313000

Reexamination Certificate

active

06898659

ABSTRACT:
An interface device according to the present invention interfaces with a host by an m-bit unit. A flag signal generator circuit generates a mode flag signal indicating whether a data transfer mode of the interface device is a multi-transfer mode. A control circuit operates responsive to information indicating whether an address from the host is a data width aligned address and whether the address thus transmitted belongs to a data width aligned address range. The control circuit causes m-bit data from the host to be continuously stored in a first-in first-out memory. Data continuously stored in the memory is at once transmitted to a high-speed bus connected to the interface device.

REFERENCES:
patent: 5535341 (1996-07-01), Shah et al.
patent: 5664117 (1997-09-01), Shah et al.
patent: 5761450 (1998-06-01), Shah
patent: 5978866 (1999-11-01), Nain
patent: 6292862 (2001-09-01), Barrenscheen et al.
patent: 00157924 (1998-08-01), None

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