Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-05-01
2002-12-24
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S712000, C438S745000
Reexamination Certificate
active
06498107
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to the formation of thin films, and, more particularly to the formation of thin dielectric films by gas-cluster ion-beam (GCIB) on surfaces rendered free of native oxides to assure high quality interfacial layers and films.
The use of a GCIB for etching, cleaning, and smoothing of the surfaces of various materials is known in the art (See for example, U.S. Pat. No. 5,814,194, Deguchi, et al., “Substrate Surface Treatment Method”, 1998). Means for creation of and acceleration of such GCIBs are also described in the Deguchi reference. It is also known (U.S. Pat. No. 5,459,326, Yamada, “Method for Surface Treatment with Extra-Low-Speed Ion Beam”, 1995) that atoms in a cluster ion are not individually energetic enough (on the order of a few electron volts) to significantly penetrate a surface to cause the residual sub-surface damage typically associated with the other types of ion beam processing in which individual ions may have energies on the order of thousands of electron volts. Nevertheless, the cluster ions themselves can be made sufficiently energetic (some thousands of electron volts), to effectively etch, smooth or clean surfaces as shown by Yamada & Matsuo (in “Cluster ion beam processing”,
Matl. Science in Semiconductor Processing I
, (1998) pp 27-41).
The heart of high-density memory and microprocessor chips is a very thin film of an electrically insulating material formed on the surface of a silicon crystal wafer. This insulator, referred to as the gate dielectric, must sustain very high electric fields and serve efficiently as the key component in the storage of electrical charge. A conductor film, not necessarily a true metal, must then be formed on top of the dielectric. Two basic types of microelectronic devices are fabricated from these so-called metal/insulator/silicon (MIS) layered structures, namely bit storage or “memory”, and logic transistors. An assembly of many bit-storage units on a single silicon wafer is used to fabricate dynamic random-access memory (DRAM) integrated circuits, while an assembly of many logic transistors is used to fabricate microprocessors. As the chip industry moves toward smaller circuit elements packed more tightly on the chip, it is required that the area devoted to each charge-storage circuit on the chip be not only smaller but also store at least the same amount of charge. Two approaches are possible, first the thickness of the gate dielectric film can be reduced and second the intrinsic storage ability of that insulator, called its dielectric constant, can be increased by choice of a new kind of material. Up until the present time, the chip industry has used silicon oxide (nominally SiO
2
, referred to as silica or just “oxide”) as the dielectric and has succeeded in making each chip generation with thinner oxide films. When the insulator is this oxide, then the structures consisting of a conductor (metal or polysilicon) film, on an oxide film, in turn on silicon, is the metal/oxide/silicon (MOS) structure employed as the basic building block unit of the vast majority of the semiconductor industry product. But the trend of continuing to reduce the thickness of the oxide film in the MOS is projected to run out of potential as it reaches basic physical limits.
Silicon oxide thin films have been the basis for gate dielectrics in silicon-based very large scale integration (VLSI) complementary metal-oxide semiconductors (CMOS) for several decades now. As the industry moves toward more advanced devices, the gate dielectric thickness is reduced with each design generation but will soon reach what is believed to be an ultimate limit. When the physical thickness of any dielectric material is less than about 5 to 15 Å, direct quantum tunneling across this dielectric barrier results in sufficient current (leakage) as to cause the CMOS transistors to malfunction. CMOS now being developed for production manufacture and marketing in the near future, will utilize oxide films at about this critical thickness. Thinner films of oxide cannot be used in future generations of CMOS technology, no matter what their composition or state of matter. The physical thickness of the film must be kept greater than this approximate amount.
Research into new materials has suggested that a compound known as silicon nitride (nominally Si
3
N
4
) may be used for a gate dielectric with a higher dielectric constant. In a CMOS structure when the dielectric is other than silicon oxide, the layer stack of gate/dielectric/silicon is referred to as metal/insulator/silicon or MIS. The dielectric constant (&kgr;) for Si
3
N
4
is about 4.2 compared with about 2.13 for SiO
2
, at low frequencies. Considerable effort has already been expended on developing apparatus and methods to fabricate thin silicon nitride films. While material quality has improved, it appears that heretofore it has not been possible to avoid having the quality of this material compromised by either poor atomic structure, unsatisfactory stoichiometry (ratio of number of silicon atoms to those of nitrogen), or unwanted impurities such as oxygen or hydrogen. This has delayed the introduction of such films and now it is less clear that the modest increase in physical thickness will result in the necessary advantage for CMOS device performance in future generations.
Metal-oxide compounds of many kinds, mainly those utilizing transition metals, have potentially useful dielectric properties as well as compatibility with silicon wafers and the fabrication processes required to construct VLSI CMOS devices. There are a wide variety of materials being evaluated at present for this application, which can be grouped according to the approximate magnitude of their dielectric constant. So-called medium-&kgr; materials include: Ta
2
O
5
, CeO
2
, TiO
2
, ZrO
2
, HfO
2
, and (Al,Zr)O
2
. (Al,Zr)O
2
can be formed with many ratios of Al to Zr content (as in a metal alloy). For these, the &kgr; ranges from ~10 to 50, with 28 for ZrO
2
and HfO
2
being typical. These latter are known to provide films that at physical thickness of 50 Å function in thin-film MIS capacitors with effective (oxide-like) thickness of about 10 Å. Other metal-oxide compounds are dielectrics with much larger &kgr;, the so-called high-&kgr; materials. Among these BaTiO
3
, SrTiO
3
, PbTiO
3
, ZrTiO
3
and the alloys (Ba,Sr)TiO
3
and (Pb,Zr)TiO
3
are known to have &kgr; in excess of 100 and in single crystals in excess of 1000. Film deposition and processing difficulties presently limit the introduction of these dielectrics into CMOS technology.
Oxide dielectric films on silicon of the best quality are grown at elevated temperature by reaction of environmental oxygen or oxygen-containing gasses with the silicon surface, i.e., so-called thermal oxidation. All of the dielectrics with larger &kgr; must be deposited and this introduces several difficulties. One of these difficulties is that the metal-oxide compounds that compose these dielectrics will themselves react with the silicon forming a compound of metal, silicon, and oxygen in a thin layer at the interface (H. Ono and K.-I. Koyanagi in “Formation of Silicon-Oxide Layers at the Interface Between Tantalum Oxide and Silicon Substrate”,
Applied Physics Letters
, Vol. 75, pp. 3521-3523 (1999)). These interfacial layers often are poor quality dielectrics with either reduced &kgr;, are somewhat conducting or have a high density of charge trapping sites. Also, any appreciable thickness of this layer will then reduce the overall effective dielectric effect of the capacitor in the CMOS device and hence the deposited film must be reduced in thickness to achieve the required capacitance, and this in turn counters the intent of using the higher-&kgr; film material.
One nearly ideal construction for metal-oxide dielectric films on silicon is to have a single atomic layer (i.e., a monolayer) of some suitable element terminating the silicon at the interface. Hydrogen and nitrogen are two known suitable elements for silicon te
Cohen Jerrt
Epion Corporation
Kunemund Robert
Perez-Ramos Vanessa
Perkins Smith & Cohen LLP
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