Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1998-05-07
2001-01-09
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S082000, C326S086000
Reexamination Certificate
active
06172525
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to interface circuits for binary signal processing devices. More particularly, the invention relates to a slew rate control aspect of such interface circuits.
2. Description of the Prior Art
Numerous circuit applications require an interface circuit, such as an input circuit or an output circuit, for transferring a logic value between two terminals. In the simplest form, a drive transistor has a control electrode coupled to a first terminal and main current path which couples the second terminal to a selected power supply. When a signal received at the first terminal turns the drive transistor on, the other terminal is pulled to the potential of the power supply. In this way, the second terminal can be supplied with a different current than the driving signal at the first terminal.
One common use for interface circuits is for binary signal processing devices, such as standard and programmable logic devices. These devices have a core with a great number of logic arrays each of which output a logic signal that must be coupled to associated input/output pins of the device. The purpose of interface circuits is to ensure that data is communicated correctly with other devices, such as over a communication bus, and these circuits are accordingly designed to withstand dangers which they may reasonably be expected to encounter.
A commonly used interface circuit is a tri-state output buffer, which is characterized by its three possible output states: “low”, “high” and “tri-state”. The typical tri-state buffer has an output terminal, a pull-up device to selectively couple the output to a first supply and a pull-down device to selectively couple the output to a second, lower supply. The buffer is in the “tri-state” mode when both of the pull-up and pull-down devices are in the non-conductive “OFF” state, thereby presenting a high impedance to the output.
U.S. Pat. No. 5,500,611 (Popat et al) shows a tri-state output buffer with a high and a low power mode. The low power mode is provided by a weak pull up device and is used in a sleep mode, while the high power mode is provided by a strong pull up device. Both pull-up devices include normally cut-off FET's with a main current channel coupled to an output node and to a supply terminal. The strong pull-up device differs from the weak pull up device in that when the FETs are enabled the main current path of the weak pull-up device has a higher resistance than the main current path of the strong pull up device. Thus, when the weak pull up device is activated, its higher resistance provides a smaller current to the output pin than when the strong device is activated, in a ratio of 1:4. The different resistances are obtained through selection of different lengths and widths of the main current paths of the FETS.
In binary signal processing devices having a large number of output pins and associated interface circuits, power surges are possible when a large number of drive transistors are nearly simultaneously enabled, due to switching transients. However, minimizing power consumption whether in the steady state as in Popat or during switching often conflicts with minimum current requirements for external devices connected to the interface circuit. For example, standards for communication buses often have minimum current levels to be maintained. A PCI bus must maintain an AC drive current of −40 mA pull-up and 53 mA pull-down.
SUMMARY OF THE INVENTION
Generally speaking, according to the invention, an interface circuit includes an input terminal for receiving an input signal, an output terminal, and a drive transistor having a main current path coupling the output terminal to a power supply. A slew rate control device has an impedance selectively coupleable between said input terminal and a control terminal of said drive transistor to selectively control the switching speed of said drive transistor and the slew rate of the signal at the output terminal relative to the input signal. Slew rate is a measure of the rate of change of the output signal in response to a change in the input signal. With the impedance between the input terminal and the control gate, the voltage rise (or fall) at the control gate is slowed, as compared to the absence of such impedance, upon transition of the input signal, so the switching speed of the drive transistor as reduced.
The aim of Popat was to provide a device with a low power consumption in a sleep mode. It is noted that the low and high power modes also correspond to a low and a high slew rate in Popat. Popat's strong and weak pull-up devices effectively couple a different resistance between the output node and the supply rail, so that the output node will be pulled up faster when the strong pull-up device is enabled than when the weak pull-up device is enabled. However, the current supplied to the output pin is directly dependent on the slew rate in the steady state, as it depends on the selected characteristic of the FET's main current channel.
By contrast, in the present invention, the current supplied to the output node is not dependent on the slew rate. Rather the slew rate is controlled by an impedance placed between the input node and the control terminal of the drive transistor. The output node is still coupled to the supply rail by the main current channel, but now a slow slew rate can be obtained with a drive transistor having a low resistance main current path. Consequently, the drive transistor can be selected to provide a steady state output current of a desired level to an external device, such as a bus, while having a desired slew rate based on the selection of the impedance placed between the input node and the control terminal of the drive transistor.
Additionally, in the present invention multiple slew rates may be achieved with only one drive transistor by interposing multiple selectable impedances between the input terminal and the control gate of the drive transistor, whereas the device of Popat requires a different drive transistor for each slew rate. Such impedances are provided in an embodiment by slew rate control transistors coupled in parallel between the input terminal and the control gate of the drive transistors. The main current paths of the slew rate control transistors have different resistances which, when coupled with the gate capacitance of the drive transistor, provides an impedance. Different impedances are obtained by selectively enabling the slew rate control transistors. Multiple slew rates can be implemented in the device according to the invention with lesser die area, as the resistive slew rate transistors present between the input node and the control terminal of the drive transistor can be smaller since they are not in the supply current path.
According to a favorable embodiment, a pass gate is coupled between the input terminal and a control terminal of the drive transistor and is switchable between an enabled state, in which the pass gate exhibits a selected resistance, and a disabled state, in which the pass gate presents an open circuit. A slew rate control input is coupled to control terminals of the pass gate to control switching of the pass gate between the enabled and disabled states. When switched to the enabled state, the resistance of the pass gate coupled with the gate capacitance of the drive transistor provides an RC time constant which slows the rate of change of the voltage at the drive transistor's control terminal arising from a transition of the input signal. Favorably, a second pass gate, having a second resistance different from the first resistance, is coupled electrically in parallel with the first pass gate between the input terminal and the control terminal of the drive transistor. The two pass gates are selectively enabled to implement a variable resistance between the input terminal and the control terminal of the drive transistor.
A particular advantage of the use of pass gates as resistors is that pass gates have a PMOS and an NMOS devi
Philips Electronics North America Corporation
Piotrowski Tony E.
Tokar Michael
Tran Anh
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