Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2008-07-29
2008-07-29
Tran, Anh Q (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C326S037000
Reexamination Certificate
active
07405587
ABSTRACT:
Provided is an interface circuit having a terminator, in which the terminator includes parallel-connected first to an Nthresistance elements, where N is an integral number equal to or more than 2, and a first to an nthcut-off elements connected in serial with each of the corresponding n(1≦n<N) first to the Nthresistance elements of the first to the Nthresistance elements.
REFERENCES:
patent: 5151611 (1992-09-01), Rippey
patent: 5510727 (1996-04-01), Culmer et al.
patent: 6147520 (2000-11-01), Kothandaraman et al.
patent: A-2003-270299 (2003-09-01), None
Furuya Yasunari
Komatsu Fumikazu
Oliff & Berridg,e PLC
Seiko Epson Corporation
Tran Anh Q
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