Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1995-06-29
1996-09-10
Westin, Edward P.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
375356, 327145, 327155, H03K 1900
Patent
active
055552137
ABSTRACT:
An interface circuit (100) for interfacing an electronic device, such as a microprocessor (102), operating at a device clock speed and a finite synchronous state machine (104) comprised of a D-type flip-flop (106) and a synchronous state machine (108), which are operating at a state clock speed, is provided. The device clock speed being capable of being greater than the state clock speed. The interface circuit.degree. (100) comprises an input circuit, which may comprise a first NAND gate (120), connected to a latch circuit which may comprise interconnected second and third NAND gates (124) and (126). The input circuit and latch circuit store an input signal (121) received from the electronic device and transmit the input signal (121) to the flip-flop (106) when the synchronous state machine (108) is ready to accept further input signals. A system for operating the finite synchronous state machine (104) associated with a state clock speed and a method for interfacing an electronic device operating at a device clock speed and a synchronous state machine (108) operating at a state clock speed are also provided.
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Hewitt S. R.
Patti C. B.
Rockwell International Corporation
Roseen Richard
Westin Edward P.
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