Interface circuit for using in high-speed semiconductor...

Details Interface circuit for using in high-speed semiconductor... Interface circuit for using in high-speed semiconductor...

2000-11-30

2002-11-19

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S083000, C365S068000

Reexamination Certificate

active

06483766

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an interface for a semiconductor device, and more particularly to an interface circuit and an interfacing method suitable for a high-speed semiconductor device.
2. Discussion of Related Art
As the operational speed of semiconductor chips increase, the need for a low power supply voltage and high-speed interface-circuits also increase. A lower supply voltage decreases power dissipation and reduces transmission line effects in high-speed operations. There has been a trend towards decreasing the power supply voltage applied to high speed semiconductor chips, for example, from 5 volts (V) to 3.3V, 2.5V, or less than 2.5V. For example, for a highly integrated semiconductor device having a gate poly size of less than 0.18 &mgr;m, and employing a dual oxide manufacture process to form a thin tunnel oxide, the internal power supply voltage is about 1.8V. Integrated circuit chips typically include an internal voltage controller for dropping the external power supply voltage applied from an exterior to the internal voltage needed for internal circuits. For example, a random access memory (RAM) is described with a voltage reduction circuit mounted as an internal voltage controller for reducing the voltage applied to an internal circuit in Japanese Patent Publication No.
9-270191.
An input receiver can be used as an interface circuit for buffering an external signal to a level appropriate for the internal circuits of a semiconductor chip. As its name implies, an interface circuit operates between the internals of an integrated circuit and any external components. The voltage levels output, and setup and hold times are important parameters of an input receiver.
Typically, the input receiver is designed to have a signal interface such as a LVTTL, HSTL, or GTL, according to the needs of the particular semiconductor device. The LVTTL interface is commonly used in current designs.
For example, an LVTTL interface wherein the external power supply voltage (hereinafter, EXTVDD) is 3.3V (or 2.5V), while the internal power supply voltage is 1.8V or some voltage less than EXTVDD. The reduced internal voltage provides a decrease in transition time with increased speed and a decreased operation current.
However, in the case of an internal power supply voltage less than EXTVDD-1Vt (Vt is a threshold voltage), the rising/falling time of an input signal is about 1v/1n, and a high level of the input signal is higher than the internal power supply voltage+1Vt, there is a problem in that the setup and hold time cannot be satisfied with accuracy. That is, when the level of the internal power supply voltage is about 1.8V, with a swing between Vil=0V and Vih=3V, and the rising/falling time of the input signal is about 1v/1n, the input receiver operates only when the level of the input signal is less than the internal power supply voltage-1vt at a transition from the high level to the low level. Accordingly, the rising/falling time of 1v/1n and the voltage swing at the LVTTL interface makes satisfaction of the setup/hold time tSU/tHD and optimization of a current consumption difficult.
Conventional input receivers are explained with reference to
FIGS. 1
to
3
.
FIG. 1
shows an input receiver which includes p type and n type channel metal-oxide semiconductor (MOS) transistors PM
1
, PM
2
, NM
1
, NM
2
, a p-type channel MOS transistor PM
3
and an inverter chain
20
. The inverter type input receiver receives an input signal XAi through gates of the p type and n type channel MOS transistors PM
2
, NM
1
. A control signal ZZB applied to the gate of NM
2
puts the receiver in a waiting current mode. When the control signal ZZB is applied at a level turning on the MOS transistor NM
2
and the input signal XAi is applied at a low level. Node NO
1
is pulled up to EXTVDD at a logic “high”, which is applied to inverter I
1
of the inverter chain
20
. An internal power supply voltage IVC is applied to the inverter chain
20
. Although the inverse output signal is buffered to the level of the internal power supply voltage by the inverter chain
20
and a delay of the output signal OUT is adjusted to suit a phase of a clock signal, the delay is difficult to adjust accurately for each transition. For example, when a rising/falling time of the input signal (hereinafter RFF) is 1v/1n and the input signal swings between OV and 3V (here, the external power supply voltage is 3.3V and the internal power supply voltage is 1.8V), H-L time (or L-H time) becomes “1.5ns(EXTVDD-IVC)+PMOS Vt/RFT” in order to turn on PMOS at the first stage of the inverter (or the second stage), and therefore application of this receiver in a high-speed semiconductor device is not suitable. Accordingly, as shown in
FIG. 1
, when the input signal XAi is changed from low level to high level (or vise versa), it is difficult to adjust each delay. In addition, when the internal power supply voltage is less than EXTVDD—1Vt and a rising/falling time of an input signal is large and a high level of the input signal is more than the internal power supply voltage+1Vt, the above described input receiver cannot meet the setup/hold time tSU/tHD requirements.
With respect to
FIG. 2
, an amplifier type input receiver is shown for sensing voltage, including an inverter chain
20
and a current mirror type differential amplifier including P type and N type channel MOS transistors PM
10
, PM
11
, NM
10
, NM
11
, NM
12
, and NM
13
. In the input receiver shown in
FIG. 2
, an input signal XAi is input to a gate of n type channel MOS transistor NM
10
as the first input signal, and a reference signal REFi is input to a gate of n type channel MOS transistor NM
11
as the second input signal. The reference signal REFi and a control signal ZZB are applied to the gates of the n type channel MOS transistors NM
12
, NMI
3
, respectively. The current mirror type differential amplifier CDA functions as a voltage sense amplifier for sensing voltage. Here, the reference signal REFi is a reference voltage signal formed in a semiconductor device. As in
FIG. 1
, the input receiver structure of
FIG. 2
also has a problem when the internal power supply voltage is less than EXTVDD—1Vt, a rising/falling time of an input signal is large, and a high level of the input signal is more than the internal power supply voltage+1Vt. That is, where an output signal at an output node NO
11
of the sense amplifier is applied to the delay chain
20
to be changed to a level of the internal power supply voltage. A driving capability of a driver transistor constituting the delay chain can be variable when the output signal of the sense amplifier CDA is changed from the high level to the low level.
With respect to
FIG. 3
, similarly to
FIG. 2
, an input receiver is shown which includes an inverter chain
20
and a current mirror type differential amplifier CDA including an inverter
110
and p type and n type channel MOS transistors PM
10
, PM
11
, NM
10
, NM
11
, NM
13
. The input receiver shown in
FIG. 3
receives an input signal XAi through a gate of the n type channel MOS transistor NM
10
as the first input signal, and receives an inverted signal of the input signal XAi through a gate of the n type channel MOS transistor NM
11
as the second input signal. To a gate of the n type channel MOS transistor NM
13
acting as a current source is applied a control signal ZZB. This current mirror type differential amplifier CDA functions as a voltage sense amplifier for sensing voltage. The input receiver of
FIG. 3
has a driving power supply for the differential amplifier CDA and an inverter inverting the first input signal Xai. The input receiver is powered by the external power supply voltage EXTVDD, and a driving power supply of the delay chain
20
receiving an output signal at the output node NO
11
of the sense amplifier is powered by the internal power supply voltage, whereby this also has the same problem as mentioned with respect to
FIGS. 1 and 2
.
Accordingly, a n

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