Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2000-12-01
2002-07-09
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S086000, C326S080000, C326S056000, C327S333000
Reexamination Certificate
active
06417696
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to input/output buffers generally and, more particularly, to an interface circuit for providing gate oxide over-voltage protection to a mixed voltage I/O buffer.
BACKGROUND OF THE INVENTION
The trend in modern central processing units (CPUs) and microprocessors is to reduce the power supply operating voltage in order to reduce power consumption and increase chip density. Power supply reduction may impact other performance considerations. Due to design considerations, memory devices, such as dynamic random access memories (DRAMs), may operate at a different supply voltage than the CPU. Some devices also may be required to use more than one power supply voltage. For example, a CPU related device can respond to a signal at one voltage while other devices require another voltage. The signals can be generated by one circuit and received by another circuit.
One such configuration occurs with modern microprocessors that operate with a nominal power supply voltage of about 2.5V (or lower) while other circuits in the computer operate with a power supply voltage of about 3.3V. To facilitate communication between devices operating at different voltages, an input/output driver circuit is used.
Referring to
FIG. 1
, a diagram illustrating a conventional method of limiting an input voltage level to an input buffer is shown. In the conventional method, an NMOS transistor
10
is placed in series between a pad
12
and an input buffer
14
. The gate of the NMOS transistor
10
is connected to a supply voltage VCC. The use of the NMOS transistor
10
to limit voltage can degrade voltage levels at the input terminal of the input buffer.
The degraded voltage levels can result in increased static and dynamic currents in the input buffer
14
. Such a degration is especially true in an input buffer designed in low voltage technologies (e.g., 2.5V or less) since the threshold voltage does not scale proportionately with voltage. The voltage degradation will reduce the noise margin for the input buffer
14
. The NMOS transistor needs a thick gate oxide requiring dual gate oxide technology.
It would be desirable to provide an interface block between the PAD
12
and the input buffer
14
. Such an interface block would preferably take all the input voltage from 0V to >=Vcc+|vtp|(voltages >=Vcc+|Vtp| seen as an overvoltage condition) as seen at PAD
12
and output a voltage from 0v to Vcc. Such an interface should not draw undesired large (>1&mgr;A) currents from the PAD
12
or components (e.g., an input/output buffer).
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal having a first voltage level and a first control signal in response to (i) an input signal having a second voltage level, (ii) an enable signal, and (iii) a plurality of node voltages. The second circuit may be configured to generate the plurality of node voltages in response to the first control signal. The first circuit may be configured to limit the first voltage level.
The objects, features and advantages of the present invention include providing an interface circuit for a mixed voltage I/O buffer that may (i) provide gate oxide protection, (ii) have no active voltage degradation, (iii) reduce static and dynamic currents, (iv) maintain a comparable noise margin in a low voltage circuit, (v) use different overvoltage detection thresholds for input and output buffer operation, (vi) provide early detection of an overvoltage condition at an input pad for an input buffer operation, (vii) provide sufficient safety margin for voltage level across an input buffer's gate oxide, (viii) provide early detection of an overvoltage condition that may compensate for the delay of overvoltage detection, (ix) provide improved speed of overvoltage detection, (x) provide fast removal of residual stored charge, (xi) reduce gate oxide stresses and improve circuit recovery from an over voltage condition, (xii) fit well for both input and output buffers, and/or (xiii) operate equally well for a number of voltage differences (e.g., 2.5V-3.3V, 1.8V-2.5V, etc.).
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Cypress Preliminary Ultra37000™ CPLD Family, 5V, 3.3V, ISR High-Performance CPLDs, Cypress Semiconductor Corporation, Aug. 13, 1999, pp. 1-65.
Christopher P. Maiorana P.C.
Cypress Semiconductor Corp.
Tan Vibol
Tokar Michael
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