Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2002-09-18
2004-08-17
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S085000, C326S086000, C327S109000
Reexamination Certificate
active
06777976
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an interface circuit for transferring signals and/or data, and particularly to an interface circuit for driving a signal/data bus line terminated in accordance with an active termination scheme. More particularly, the present invention relates to an interface circuit for transferring data of a semiconductor memory device at high speed.
2. Description of the Background Art
With progress of a semiconductor technology in recent years, operation frequencies of semiconductor chips have been remarkably improved. At present, central processing units (CPUs) operating in a GHz (giga hertz) class are available. For constituting a system, it is necessary to assemble various semiconductor devices such as a CPU and a semiconductor memory device on a motherboard, and to connect these semiconductor devices together via on-board interconnection lines. The on-board interconnection lines (wires) have larger interconnection widths and larger parasitic capacitances than interconnection lines inside the chip. Also, an on-board parasitic capacitance is present. Therefore, fast transfer of signal/data is difficult. Accordingly, the signal/data transfer only at a rate of about 100 MHz or lower can be achieved at the motherboard level. For this reason, a DDR (Double Data Rate) mode has been generally and widely used. In the DDR mode, data/signal is transferred in synchronization with both rising and falling edges of a transfer clock signal so that the signal/data is transferred at a doubled rate of the transfer clock signal.
Even in the signal/data transfer scheme according to the DDR mode, it has been attempted to achieve faster data/signal transfer by increasing the transfer frequency.
FIG. 44
shows by way of example a structure of a conventional memory system. In
FIG. 44
, the memory system includes memory units MU
1
and MU
2
as well as a chip set CH performing data access to these memory units MU
1
and MU
2
. A data bus DB includes data bus lines DDBL for transmitting data DQ
0
-DQ
63
of 64 bits and a strobe signal line SDBL for transferring a data strobe signal DQS providing strobe timing of data at chip set CH.
Memory units MU
1
and MU
2
are alternatively activated to transfer data of 4 bits. In this memory system, therefore, further memory units are connected to data bus DB, for transferring data of 60 bits. For the sake of simplicity,
FIG. 44
representatively shows memory units MU
1
and MU
2
transferring data DQ
0
-DQ
3
of 4 bits.
Each of memory units MU
1
and MU
2
is formed of a DIMM (Dual Inline Memory Module), in which memory chips are mounted on front and rear surfaces of a module substrate. In
FIG. 44
, opposite sides of each module substrate are represented by left and right sides L and R, respectively. Memory unit MU
1
includes memory chips ML
1
-MLn mounted on a left side L
1
and memory chips MR
1
-MRn mounted on a right side R
1
. Likewise, memory unit MU
2
includes memory chips ML
1
-MLn mounted on a left side L
2
and memory chips MR
1
-MRn mounted on a right side R
2
. Each of memory chips ML
1
-MLn and MR
1
-MRn sends and receives 4-bit data DQ
0
-DQ
3
and data strobe signal DQS when selected.
When memory unit MU
1
or MU
2
transfers data to chip set CH, data strobe signal DQS is transferred in synchronization with the data to chip set CH from the memory chip sending the data.
Each of bus lines DDBL and SDBL of data bus DB is terminated with a termination voltage Vtt. This termination voltage is at a level of voltage VDDQ/2 intermediate between a power supply voltage VDDQ and a ground voltage. This termination voltage Vtt is supplied from a dedicated power supply circuit on the motherboard.
FIG. 45
is a signal waveform diagram illustrating an operation of transferring data from a memory unit in the memory system to the chip set shown in FIG.
44
. Memory units MU
1
and MU
2
transfer data DQ in synchronization with rising and falling edges of a clock signal CLK when selected. For detecting the rising and falling edges of clock signal CLK, complementary clock signals CLK and /CLK are used, and the detection of the clock signal edges is performed within memory units MU
1
and MU
2
based on crossing portions of complementary clock signals CLK and /CLK.
Each of bus lines DDBL and SDBL of data bus DB is kept at termination voltage Vtt through a termination resistance in a standby state. By transferring data DQ in synchronization with the rising and falling edges of clock signal CLK, it is possible to transfer data at a double rate as compared to the Single Data Rate (SDR) mode, in which data is transferred in synchronization with only the rising or falling edge of the clock signal. Such fast data transfer makes the conditions of set-up and hold times of data severer. Data strobe signal DQS is used for accurately sampling the data by chip set CH.
This data strobe signal DQS indicates a position of the clock signal, where the data transfer is performed. The memory unit transferring data once sets data strobe signal DQS to L level before the data transfer, and thereafter toggles it between H- and L levels in synchronization with the clock signal for transferring data DQ in synchronization with data strobe signal DQS. Since data bus DB is terminated at termination voltage Vtt, the data transferring chip (memory chip or chip set) drives the data bus to H- or L level.
The bus topology shown in
FIG. 44
has been generally used in a memory system including a DDR-SDRAM (Double Data Rate Synchronous DRAM). However, in order to feed the termination voltage Vtt, a chip dedicated to production of termination voltage Vtt must be arranged on the motherboard. Also, a termination resistance must be arranged for supplying the termination voltage Vtt to each of bus lines DDBL and SDBL of data bus DB. This termination resistance is formed of a pure resistance of a high resistance, and a considerable area on the motherboard is required for arranging the termination resistance to each bus line.
For overcoming the disadvantages of the bus termination scheme described above, an active termination scheme has been proposed.
FIG. 46
schematically shows a conventional system structure of an active termination scheme.
FIG. 46
representatively shows a structure of a portion related to data bus line DDBL of one bit.
In each of memory units Mu
1
and MU
2
, internal memory chips include output drive circuits ODK. Output drive circuit ODK is arranged as a final output stage in each memory chip. Data bus line DDBL is not connected to a termination resistance.
Chip set CH includes an output drive circuit ODK for driving data bus line DDBL for transferring output data, a differential amplifier circuit AMP
1
for amplifying a difference between a signal on data bus line DDBL and a reference voltage Vref, a differential amplifier circuit AMP
2
for amplifying a difference between a strobe signal STR and reference voltage Vref, and a latch circuit LKT for latching an output signal of differential amplifier circuit AMP
1
in response to an output signal of differential amplifier circuit AMP
2
.
Latch circuit LKT includes a first latch entering a latch state when the output signal of differential amplifier circuit AMP
2
is at an H level (logical high level), and a second latch entering a latch state when the output signal of differential amplifier circuit AMP
2
is at an L level (logical low level). These first and second latches commonly receive the output signal of differential amplifier circuit AMP
1
. These first and second latches alternately operate to take in and latch the data, which are transferred in synchronization with the rising and falling of data strobe signal DQS. Differential amplifier circuits (AMP
2
) may be provided corresponding to each of the first and second latches for controlling operations of these latches.
FIG. 46
shows a signal STR for representing that any one of the above structures may be employed. Strobe signal STR corresponds to data strobe signal DQS.
FIG. 47
schematically s
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