Interface circuit and operating method thereof

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor

Reexamination Certificate

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C326S083000

Reexamination Certificate

active

06452422

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an interface circuit which transmits a digital signal at a high speed.
2. Description of the Related Art
Recently, it is increasingly demanded that interface circuits, employed in I/O sections of semiconductor integrated circuits, be operated at a high speed with less noise. Examples of high-speed interface circuits are a small-amplitude differential output circuit, typically known as an LVDS (Low Voltage Differential Signalling), and a small-amplitude output circuit, typically known as a GTL (Gunning Transceiver Logic) or an HSTL (High Speed Transceiver Logic).
FIG. 1
is a circuitry diagram showing the structure of an example of an LVDS type interface circuit. The first example of the interface circuit comprises: a drive circuit
7
which differentially outputs an output signal in accordance with an input signal V
IN
to a terminating resistor R
L
connected between two output terminals D
O
and X
DO
; and a bias circuit
6
which controls an output current I of the drive circuit
7
.
The drive circuit
7
comprises: a buffer
71
which performs non-inverting output of an input signal V
IN
; an inverter
72
which performs inverting output of an input signal V
IN
; a P-channel MOSFET (hereinafter referred to as an P-MOSFET) P
11
and an N-channel MOSFET (hereinafter referred to as an N-MOSFET) N
11
which are driven by the buffer, a P-MOSFET P
12
and an N-MOSFET N
12
which are driven by the inverter, and a P-MOSFET P
C11
which serves as a constant current source for making a predetermined output current flow to the terminating resistor R
L
connected between the two output terminals D
O
and X
DO
.
The bias circuit
6
comprises: a fixed resistor R
P11
; and a P-MOSFET P
X11
which constantly controls a current I
RP
to flow to the fixed resistor R
P11
.
In such a structure, when the input signal V
IN
is at a low level, the P-MOSFET P
11
is ON, and the N-MOSFET N
11
is OFF, the P-MOSFET P
12
is OFF, and the N-MOSFET N
12
is ON. Thus, as described iwth arrow D in FIG.>
1
, the output current I flows through a path along the P-MOSFET P
C11
, the P-MOSFET P
11
and the N-MOSFET N
12
. At his time, a low level voltage (V
CL
) is out put to the output terminal D
O
, whereas a high level voltage (V
OH
) is out put to the output terminal X
DO
.
In the first example of the interface circuit, the P-MOSFET P
X11
and the P-MOSFET P
C11
operate in their saturation range, and the dimensions of the respective transistors are designed such that constants of the transistors are set at a predetermined ratio. In this structure, the P-MOSFET P
X11
and the P-MOSFET P
C11
operate under the Miller effect, thus a current I
RP
flowing through the P-MOSFET P
X11
and a current I flowing through the P-MOSFET P
C11
are in proportion to each other
Accordingly, when having the structure of the bias circuit
6
as shown in
FIG. 1
, any variation in the current I
RP
which may occur as a result of a variation in the source voltage V
DD
or any difference (deviation) occurring in transistors in the manufacturing processes can be reduced. In addition, a variation in the output current I of the drive circuit
7
which is in proportion to the current I
RP
of the bias circuit
6
can be reduced.
FIG. 2
is a circuitry diagram showing the structure of the second example of an interface circuit which is disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H3-283713. The second example of the interface circuit shown in
FIG. 2
comprises: a drive circuit
9
comprising a P-MOSFET P
15
and an N-MOSFET N
13
which are connected in series between a power source V
DD
and a ground potential; an NAND circuit
83
which supplies the P-MOSFET P
13
in the drive circuit
9
with a gate voltage V
PO
; a NOR circuit
84
which supplies the N-MOSFET N
13
with a gate voltage V
NG
; and a sense amplifier
81
and a sense amplifier
82
which control a voltage of an output terminal D
O
in the drive circuit
9
to be in a predetermined value. The output terminal D
O
is connected to a reference voltage V
TT
along a transmission path via a terminating resistor R
L
.
In such a structure, a control voltage V
OH
for controlling a voltage of the output terminal D
O
in the drive circuit
9
into a high level is input to a non-inverting input terminal of the sense amplifier
81
serving as a differential amplifier. A control voltage V
OL
for controlling a voltage of the output terminal D
O
in the drive circuit
9
into a low level is input to a non-inverting input terminal of the sense amplifier
82
serving as a differential amplifier.
The voltage of the output terminal D
O
is fed back to inverting input terminals of the respective sense amplifiers
81
and
82
. Thus, the sense amplifier
81
controls the voltage of the output terminal D
O
to a voltage level of V
OH
, whereas the sense amplifier
82
controls the voltage of the output terminal D
O
to a voltage level of V
OL
.
Either one of the NAND circuit
83
and the NOR circuit
84
supplies the MOSFET included in the drive circuit
9
with a gate voltage, in accordance with the conditions of the input signal V
IN
. The output voltages of the respective NAND circuit
83
and NOR circuit
84
are so controlled that their voltage values are in proportion to the value of the output voltages of the respective sense amps
81
and
82
.
Therefore, when the input signal V
IN
is at a high level, the voltage of the output terminal D
O
is controlled to be at a voltage level of V
OH
by the sense amp
81
, resulting in making the current I
H
flow to the terminating resistor R
L
. On the contrary, when the input signal V
IN
is at a low level, the voltage of the output terminal D
O
is controlled at a voltage level of V
OL
, resulting in making the current I
L
flow to the terminating resistor R
L
.
Accordingly, having controlled the output current I
L
or I
H
to flow to the terminating resistor R
L
in accordance with the conditions of the input signal V
IN
, the voltage of the output terminal D
O
varies.
In the first example of an interface circuit shown in
FIG. 1
, a variation of the current I
RP
, resulting from a source voltage variation or any difference occurring in transistors in the manufacturing processes, can not sufficiently be reduced. This entails problems that a current variation is large in the output current I and an amplification variations is also large in the output voltage.
Variations in the current I
RP
, which variations occur in the bias circuit as a result of a variation in a source voltage or any difference occurring in transistors in the manufacturing processes, will now be explained with reference to
FIGS. 3 and 4
.
FIG. 3
is a circuitry diagram showing the structural example of a bias circuit employed in an interface circuit.
FIG. 4
is a graph showing characteristics of output currents and output voltages with reference voltage of a gate voltage to be applied to the bias circuit illustrated in FIG.
3
.
In the bias circuit shown in
FIG. 3
, a P-MOSFET P
X12
and a fixed resistor R
P12
are connected in series between a power source V
DD
and a ground potential. In such a structure, when the power source V
DD
is set at 3.6 V or 2.7 V, the relationship between the current I
RP
and the output voltage V
RP
with reference to the gate voltage V
O
is as shown in FIG.
4
.
In the first example, as shown in
FIG. 1
, of the bias circuit, the gate voltage and the drain voltage of the P-MOSFET P
X11
are the same (V
GP
). Accordingly, based on the characteristics shown in
FIG. 4
, the current I
RP
is −1.9 mA when the source voltage VDD is 2.7 V, whereas the current I
RP
is −3.3 mA when the source voltage V
DD
is 3.6 V.
Accordingly, in the bias circuit having the structure shown in
FIG. 1
, when the source voltage V
DD
varies from 2.7 V to 3.6 V, the output current I of the interface circuit which is in proportion to the current I
RP
varies as well.
In the second example of the interface circuit shown in

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