Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
2001-02-05
2004-06-15
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S052000, C710S053000, C710S057000, C375S377000
Reexamination Certificate
active
06751689
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to an interface circuit for transmitting data via serial interface from and to a processor and a method for transmitting data between a serial interface and a processor.
The present invention is intended for serial, especially wireless data transmission to a processor that is arranged, for example, on a chip card. The present invention is particularly suitable for wireless data transmission between a card reader and a contactless chip card having a processor.
In these applications, the load is to be removed from the processor so that a processor can be used which is clocked slowly. This is intended to reduce the current consumption (the current consumption is proportional to the clock frequency in the processors currently used). In addition, it is intended to switch the processor to the so-called sleep or standby mode, in which the processor is not operating and thus consumes much less current, as often as possible and as long as possible.
According to the current state of the art, data is transmitted between a serial interface and a processor by a parallel/serial or, respectively, serial/parallel conversion via a so-called universal asynchronous receiver/transmitter (UART). This is usually implemented by a shift register at the end at which, for example, the transceiver for a wireless transmission is connected. This shift register can be loaded bit by bit (during reception) or, respectively, read bit by bit (during transmission). At the other end of the UART, the processor must fetch the data from the UART or, respectively, provide them to it in parallel and synchronously in time with the data transmission protocol used (see FIGS.
1
and
2
). This makes very high demands on the real-time capability of the processor. Such high demands on the real-time capability of the processor are in contradiction with the demand that the processor should consume as little current as possible and should be as inexpensive as possible. Especially in the case of contactless chip cards, processors can be used that are as simple as possible and are clocked as slowly as possible and, therefore, consume very little current and are very inexpensive. However, such processors cannot meet the abovementioned real-time requirements.
In the prior art, a method is, therefore, currently used for contactless chip cards in which the serial information is fetched from the connection of the serial interface or, respectively, written to the connection of the serial interface bit by bit by the processor. However, this task ties up a great amount of computing time of the processor so that, in turn, it becomes necessary to use a faster processor.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an interface circuit and method for transmitting data between a serial interface and a processor that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that specifies an interface circuit for transmitting data via a serial interface from and to a processor, in which the data transmission can run without loading the processor. It is also an object of the invention to specify a suitable method for transmitting data between a serial interface and a processor.
With the foregoing and other objects in view, there is provided, in accordance with the invention, an interface circuit for transmitting data via a serial interface to and from a processor. The interface circuit includes only one memory for a number of word lengths disposed between a serial interface and a processor. The memory is written to and read from word by word or bit by bit.
With the objects of the invention in view, there is also provided a method for transmitting data between a serial interface and a processor. The method includes writing received data from a serial interface into a memory bit by bit, reading the received data byte by byte from the memory to a processor, writing received data from a processor into a memory byte by byte, and reading the received data bit by bit from the memory to a serial interface.
According to the invention, this object is achieved by an interface circuit in which a memory for a number of bus or processor word lengths (e.g. bytes) is arranged between the serial interface and the processor.
The object is also achieved by a method in which the data are received serially bit by bit and are read into a memory and there are read out again byte by byte by the processor or, respectively, are written into the memory byte by byte by the processor and are transmitted byte by byte from the memory.
In this arrangement, it is especially preferred if the memory can be written to and read out word by word or bit by bit. To this end, it is especially preferred if the memory has a write pointer and a read pointer that can individually address each bit or each word (e.g. byte).
To save more current, it is advantageous if the processor has a current saving mode (sleep mode or standby mode) with minimum current consumption.
It is also advantageous to build a comparator into the memory. This removes further load from the processor.
The comparator can preferably comprise a simple logic unit that automatically compares each received bit with the content of the memory cell to which the received bit is to be written.
To further simplify the circuit, the memory can be integrated in the CPU module or in the receiver module. A further simplification of the circuit is also possible by implementing the memory by means of RAM cells from the normal RAM in the address area of the processor.
To remove further load from the processor, a checksum module can be provided in addition to the memory. In addition to the checksum module, a comparator can also be provided which compares the checksum of the received data with an expected precalculated checksum. This makes it possible to remove further load from the processor.
The memory preferably can be implemented in the form of a ring structure and/or provided with an overflow detection device that activates (wakes up) the processor in the event of an impending overflow of the memory. This makes it possible to prevent losses of data resulting from overwriting in the memory.
In the method according to the invention, it can be preferably provided, to remove load from the processor, that the write pointer and read pointer of the memory can be automatically set without the processor becoming active.
A method in which the processor can freely set the write pointer and read pointer of the memory provides much greater flexibility in the programming.
Even greater programming flexibility is provided by the method in which the processor treats the individual memory cells of the memory as components of its own address area and can thus optionally read and write to these cells.
Further load can be removed from the processor in that an automatic data comparison is provided in which the data to be expected must be stored at the corresponding place in the memory and each received bit is compared by a simple logic unit with the content of the memory cell in the memory to which it is written.
In this arrangement, the write pointer of the memory can provide both the addressing of the expected bit, with which the comparison is to be made, and the addressing of the received bit that is now to be written into the memory. This provides a simplification of the programming and of the circuit configuration.
In this arrangement, after the comparison of all bits of a byte, a bit associated with this byte can be preferably set to 0 if all bits were equal and is set to 1 if not. It is especially preferred in this arrangement if the associated bits can be accessed byte by byte by the processor. A newly received bit sequence can be evaluated rapidly and simply by masking out comparison information.
During this process, the processor can also preferably be switched to a current saving mode (sleep mode or standby mode) during the data transmission. It is then especially preferred if
Hofmann Harald
Klosa Klaus
Gaffin Jeffrey
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Peyton Tammara
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