Interface circuit and method for transmitting binary logic signa

Details Interface circuit and method for transmitting binary logic signa Interface circuit and method for transmitting binary logic signa

1997-03-28

1999-08-10

Santamauro, Jon

Electronic digital logic circuitry

Interface

Current driving

326 26, 326 86, H03K 190175

Patent

active

059364297

ABSTRACT:
An interface circuit and method for transmitting a binary logic signal from a first electronic circuit to a second electronic circuit over a transmission line coupled to said first electronic circuit by a first terminal and to said second electronic circuit by a second terminal. The interface circuit transmits the binary logic signal by transmitting a pulse at a first potential at each falling transition of the binary logic signal, and a pulse at a second potential at each rising transition of the binary logic signal. At other times, the output terminal of a driver circuit is placed in a high-impedance state. A receiver circuit outputs a first logic Level upon receiving a pulse at the first potential, and outputs a second logic level upon receiving a pulse at the second potential. Output of these logic levels is maintained until the next pulse is received. The transmission line is preferably terminated at a potential intermediate between the first and second potentials.

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"100 Mhz ni totsunyu shita maikuropurosasa, CPU bodo sekkei ga kawaru" (Microprocessors hit 100 MHz, CPU bo change), Nikkei Electronics No. 556, Jun. 8, 1992.
Center-Tap-Terminated (CTT) Low-Level, High-Speed Interface Standard for Digital Integrated Circuits, JEDEC Standard JESD8-4, Electronic Industries Association, Nov. 1993.

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