Interface circuit and method for programming or...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration

Reexamination Certificate

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C710S104000, C710S007000, C714S734000

Reexamination Certificate

active

08060661

ABSTRACT:
An interface circuit and method for programming or communicating with an integrated circuit (IC) via a power supply pin is provided herein. In general, the power supply pin may be coupled for receiving a relatively constant voltage signal during a first mode of operation (i.e., a normal mode) and a modulated voltage signal during a second mode of operation (i.e., a programming or communication mode). The interface circuit may be coupled between the power supply pin and other IC components for decoding the modulated voltage signal into data. Various encoding/decoding schemes may be used by the interface circuit and method for communicating data to the IC over the power supply lines. The decoded data may be used for programming or communication purposes.

REFERENCES:
patent: 4727514 (1988-02-01), Bhuva et al.
patent: 4734885 (1988-03-01), Luich
patent: 5163146 (1992-11-01), Antanaitis et al.
patent: 5336951 (1994-08-01), Josephson et al.
patent: 5369703 (1994-11-01), Archibald et al.
patent: 5376834 (1994-12-01), Carobolante
patent: 5418969 (1995-05-01), Matsuzaki et al.
patent: 5481549 (1996-01-01), Tokuyama
patent: 5568083 (1996-10-01), Uchiyama et al.
patent: 5594442 (1997-01-01), Paulos et al.
patent: 5629635 (1997-05-01), Reno
patent: 5661685 (1997-08-01), Lee et al.
patent: 5664205 (1997-09-01), O'Brien et al.
patent: 5693570 (1997-12-01), Cernea et al.
patent: 5726995 (1998-03-01), Wong
patent: 5748684 (1998-05-01), Sanchez
patent: 5838950 (1998-11-01), Young et al.
patent: 5877719 (1999-03-01), Matsui et al.
patent: 5878234 (1999-03-01), Dutkiewicz et al.
patent: 5925110 (1999-07-01), Klein
patent: 6038400 (2000-03-01), Bell et al.
patent: 6105155 (2000-08-01), Cheng et al.
patent: 6182163 (2001-01-01), Yamashita et al.
patent: 6191614 (2001-02-01), Schultz et al.
patent: 6195712 (2001-02-01), Pawlowski et al.
patent: 6253268 (2001-06-01), Bjorkengren et al.
patent: 6256240 (2001-07-01), Shinozaki
patent: 6260139 (2001-07-01), Alfke
patent: 6281716 (2001-08-01), Mihara
patent: 6298448 (2001-10-01), Shaffer et al.
patent: 6320809 (2001-11-01), Raad
patent: 6330231 (2001-12-01), Bi
patent: 6400605 (2002-06-01), Adkins
patent: 6429682 (2002-08-01), Schultz et al.
patent: 6499123 (2002-12-01), McFarland et al.
patent: 6509845 (2003-01-01), Tanaka
patent: 6577157 (2003-06-01), Cheung et al.
patent: 6577175 (2003-06-01), Kim et al.
patent: 6798254 (2004-09-01), Marshall et al.
patent: 6865113 (2005-03-01), Voicu et al.
patent: 6912606 (2005-06-01), Fay
patent: 6924790 (2005-08-01), Bi
patent: 6999342 (2006-02-01), Ooishi
patent: 7030668 (2006-04-01), Edwards
patent: 7089434 (2006-08-01), Kuo
patent: 7096137 (2006-08-01), Shipton et al.
patent: 7107178 (2006-09-01), Won et al.
patent: 7174144 (2007-02-01), Lin
patent: 7176726 (2007-02-01), Bock
patent: 7224801 (2007-05-01), Abdo et al.
patent: 7228476 (2007-06-01), Scipioni et al.
patent: 7269780 (2007-09-01), Arima et al.
patent: 7304923 (2007-12-01), Sano et al.
patent: 7310757 (2007-12-01), Ngo et al.
patent: 7392409 (2008-06-01), Tateyama
patent: 7392447 (2008-06-01), Tang et al.
patent: 7415624 (2008-08-01), Miller et al.
patent: 7415647 (2008-08-01), Yee
patent: 7421291 (2008-09-01), Karaoguz et al.
patent: 7424553 (2008-09-01), Borrelli et al.
patent: 7496692 (2009-02-01), Holm et al.
patent: 7508242 (2009-03-01), Tokuno
patent: 7532056 (2009-05-01), Seo
patent: 7579895 (2009-08-01), Sun et al.
patent: 7626576 (2009-12-01), Anandakumar et al.
patent: 7672258 (2010-03-01), Wu et al.
patent: 7679964 (2010-03-01), Lee
patent: 7710939 (2010-05-01), Shao et al.
patent: 7739529 (2010-06-01), Hardman et al.
patent: 7760655 (2010-07-01), Wilhelm
patent: 7795893 (2010-09-01), Agatsuma
patent: 7802212 (2010-09-01), Best et al.
patent: 7844308 (2010-11-01), Rhee et al.
patent: 2002/0108011 (2002-08-01), Tanha
patent: 2003/0031320 (2003-02-01), Fan et al.
patent: 2003/0074364 (2003-04-01), Sewall et al.
patent: 2003/0093751 (2003-05-01), Hohl
patent: 2005/0052437 (2005-03-01), Hudson
patent: 2005/0071730 (2005-03-01), Moyer et al.
patent: 2005/0093572 (2005-05-01), Sun et al.
patent: 2006/0035590 (2006-02-01), Morris et al.
patent: 2006/0212838 (2006-09-01), Carson et al.
patent: 2006/0236147 (2006-10-01), Best et al.
patent: 2008/0071972 (2008-03-01), Kimura
patent: 2008/0086626 (2008-04-01), Jones et al.
patent: 2009/0167093 (2009-07-01), Nguyen et al.
patent: 2009/0315582 (2009-12-01), Agatsuma
patent: 0619548 (1994-10-01), None
National Semiconductor, Jun. 1989, “54150/DM54150/DM741150, 54151A/DM54151A/DM74151A Data Selectors/Multiplexers” Datasheet.
The Authoritative Dictionary of IEEE Standard Terms, Seventh Edition, 2000, (selected definitions) ISBN 0738126012.
U.S. Appl. No. 12/075,633: “Encoded Acknowledge Signal for Wireless Communication,” David G. Wright, filed on Mar. 12, 2008; 28 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 12/075,633 dated Apr. 26, 2010; 11 pages.
U.S. Appl. No. No. 12/075,632: “Interrupt Latency Reduction,” David G. Wright, filed on Mar. 12, 2008; 31 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 12/075,632 dated May 25, 2010; 9 pages.
USPTO Final Rejection for U.S. Appl. No. 12/075,632 dated Feb. 3, 2010; 9 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 12/075,632 dated Jun. 24, 2009; 6 pages.
The Authoritative Dictionary of IEEE Standard Terms, Seventh Edition, 2000, (selected definitions) ISBN 0738126012; 6 pages.
Wong et al., “Flexible Test Mode Design for DRAM Characterization,” 1996 Symposium on VLSI Circuits Digest of Technical Papers, Vol., No., pp. 194-195, Jun. 13-15, 1996, doi: 10.1109/VLSIC.1996.507768; 2 pages.
USPTO Notice of Allowance for U.S. Appl. No. 12/005,775 dated Jun. 19, 2009; 6 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 12/005,775 dated Sep. 22, 2009; 4 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 12/005,775 dated Feb. 11, 2009; 5 pages.
U.S. Appl. No. 12/005,768: “Intelligent Power Supervisor,” David G. Wright, filed on Dec. 27, 2007; 43 pages.
USPTO Notice of Allowance for U.S. Appl. No. 12/005,768 dated Jun. 28, 2010; 6 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 12/005,768 dated Feb. 16, 2010; 8 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 12/005,768 dated Aug. 20, 2009; 7 pages.
USPTO Requirement for Restriction/Election for U.S. Appl. No. 12/005,768 dated May 11, 2009; 6 pages.
U.S. Appl. No. 11/973,038: “Programmable Voltage Regulator,” David G. Wright, filed on Oct. 4, 2007; 51 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/973,038 dated Jul. 1, 2010; 5 pages.
USPTO Final Rejection for U.S. Appl. No. 11/973,038 dated Mar. 25, 2010; 5 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/973,038 dated Oct. 23, 2009; 5 pages.
U.S. Appl. No. 11/973,090: “Intelligent Voltage Regulator,” David G. Wright, filed on Oct. 4, 2007; 51 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/973,090 dated Jun. 22, 2010; 7 pages.
USPTO Advisory Action for U.S. Appl. No. 11/973,090 dated May 20, 2010; 2 pages.
USPTO Final Rejection for U.S. Appl. No. 11/973,090 dated Mar. 9, 2010; 7 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/973,090 dated Sep. 21, 2009; 7 pages.
U.S. Appl. No. 12/005,774: “Intelligent Serial Interface,” David G. Wright, filed on Dec. 28, 2007; 30 pages.
USPTO Final Rejection for U.S. Appl. No. 12/005,774 dated Mar. 23, 2010; 14 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 12/005,774 dated Sep. 15, 2009; 12 pages.
U.S. Appl. No. 12/005,748: “Firmware Memory of an Integrated Circuit,” David G. Wright, filed on Dec. 28, 2007; 31 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 12/005,748 dated May 11, 2010; 14 pages.
U.S. Appl. No. 12/005,950: “Ultra Low Power Sleep Mode,” David G. Wright, filed on Dec. 28, 2007; 30.
U.S. Appl. No. 11/904,644: “Configuration of Programmable Device using a DMA Controller,” David G. Wright, filed on Sep. 28, 2007; 34 pages.
USPTO Final Rejection for U.S. Appl. No. 11/904,644 dated Apr. 28, 2010; 7 pages.
USPTO

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