Interface circuit and interface-network system using the same

Details Interface circuit and interface-network system using the same Interface circuit and interface-network system using the same

1995-04-26

1997-08-26

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 30, 326 27, 326 58, H03K 190948, H03K 190185

Patent

active

056614160

ABSTRACT:
An interface circuit includes at least one signal processing circuit connected to a transmission line which is equipped with a terminal circuit having a resistor with a terminal voltage applied to at least one terminal, and includes an input circuit for inputting from the transmission line a signal to be processed in the signal processing circuit, or an output circuit for outputting a processed signal to the transmission line or an input and output circuit for inputting and outputting a signal. The input circuit or the output circuit or the input and output circuit are incorporated in the signal processing circuit. The input circuit or the output circuit or the input and output circuit are directly connected to the transmission line, wherein the output circuit has a push-pull circuit which is directly connected to the transmission line to receive an output signal from the signal processing circuit and to have a constant output impedance which is independent of an output from the output signal. An interface system having a signal processing circuit having he interface circuit in an interface-network is disclosed. Based on the above structure, reflection noise which occurs in the interface-network system is absorbed, with an improved focusing of a waveform, and power consumption is minimized during high-speed signal transmission.

REFERENCES:
patent: 5019728 (1991-05-01), Sanwo et al.
patent: 5066873 (1991-11-01), Chan et al.
patent: 5162672 (1992-11-01), McMahan et al.
patent: 5311083 (1994-05-01), Wanlass
patent: 5378945 (1995-01-01), Partovi
patent: 5457406 (1995-10-01), Takada
patent: 5485107 (1996-01-01), Lacey et al.
"The Increasing in the Interface Speed", M. Yamada, Institute of Electronics Information and Communication Engineers of Japan, vol. 76, No. 7, Jul. 1993, pp. 721-725.

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