Interface bus protocol for managing transactions in a system...

Details Interface bus protocol for managing transactions in a system... Interface bus protocol for managing transactions in a system...

2006-10-31

2006-10-31

Ray, Gopal C. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Protocol

C710S022000, C710S052000, C710S111000, C710S305000, C712S242000

Reexamination Certificate

active

07130942

ABSTRACT:
A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, FPGA, or similar silicon devices includes a main module connected to the microprocessor bus on one side and to a COMMON-BUS inside the interface on which a cluster of peripheral modules is appended on the other side. Peripheral modules are also connected to the user macro-cells through multiple point-to-point buses to transfer signals in two directions. A set of hardware and firmware resources such as registers, counters, synchronizers, dual port memories (e.g. RAM, FIFO) either synchronous or asynchronous with respect to macro-cells clock is encompassed in each peripheral module. Subsets of the standard resources are diversely configured in each peripheral module in accordance with specific needs of the user macro-cells.

REFERENCES:
patent: 6122747 (2000-09-01), Krening et al.
patent: 0994418 (2000-04-01), None
patent: 2349487 (2000-11-01), None
“802.6 MAN based personal communications network over CATV plants” by Jong-Heon Lee (abstract only) Publication date: Mar. 1996.

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