Interface apparatus for mediating sending and receiving...

Details Interface apparatus for mediating sending and receiving... Interface apparatus for mediating sending and receiving...

2006-03-07

2006-03-07

Perveen, Rehana (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S105000

Reexamination Certificate

active

07010640

ABSTRACT:
In a CPU, a FET is turned off and power is not supplied to a power supply element of a transceiver for a period of time until predetermined initialization processing, which is implemented in a peripheral device when power is supplied via a cable from a host PC, has been concluded (i.e., a period of time until it becomes possible for the peripheral device to initiate data communication with the host PC). Thus, even if the peripheral device and the host PC are physically connected by a cable, data signals transmitted along signal lines are not relayed by the transceiver to a logic controller, whereby it in effect becomes possible to set the peripheral device in a pseudo-non-connected state with respect to the host PC.

REFERENCES:
patent: 6601124 (2003-07-01), Blair
patent: 2002/0169915 (2002-11-01), Wu
patent: A 11-194993 (1999-07-01), None
patent: A 11-245487 (1999-09-01), None
patent: A 2000-293479 (2000-10-01), None
Universal Serial Bus Specification—Revision 1.1—Sep. 23, 1998—Section 7.1.7.1: Connect and Disconnect Signaling.

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