Interdigitated layout methodology for amplifier and H-bridge...

Details Interdigitated layout methodology for amplifier and H-bridge... Interdigitated layout methodology for amplifier and H-bridge...

2005-07-12

2005-07-12

Thomas, Tom (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S206000, C257S390000, C327S410000, C438S128000, C438S199000

Reexamination Certificate

active

06917084

ABSTRACT:
A complementary output stage in integrated circuit includes a P-channel transistor (MP1) the segmented into a first group of sections (MP1-1,2 . . . 12) and an N-channel transistor (MN1) segmented into a second group of sections (MN1-1,2 . . . 12). The sections of the first group are disposed in a plurality of N-type well regions (35), respectively, and the sections of the second group are disposed in a plurality of P-type well regions (36), respectively. The sections of the first group are alternately located with respect to the sections of the second group so as to form an interdigitated output stage area of the integrated circuit including the P-channel transistor (MP1) and the N-channel transistor (MN1) so that the higher amount of heat normally generated in the N-channel transistor is dissipated over the entire interdigitated output stage area and reduces peak temperatures in the N-channel transistor.

REFERENCES:
patent: 5220187 (1993-06-01), Miyaoka et al.
patent: 5459340 (1995-10-01), Anderson et al.
patent: 5489860 (1996-02-01), Kitagawa et al.
patent: 5737170 (1998-04-01), Moyer
patent: 6566720 (2003-05-01), Aldrich
patent: 2002/0070391 (2002-06-01), Possley
Burr-Brown OPA2544 Circuit Diagram, Drawing No. CD09693, dated May 24, 1994.

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