Interdigitated and twisted word line structure for semiconductor

Details Interdigitated and twisted word line structure for semiconductor Interdigitated and twisted word line structure for semiconductor

1990-03-30

1992-03-17

Fears, Terrell W.

Static information storage and retrieval

Format or disposition of elements

365 63, 36523006, G11C 1300

Patent

active

050974416

ABSTRACT:
A higher packing of cells in a memory circuit includes a plurality of word line drivers employing a plurality of word lines, a plurality of bit lines, and various decoders. Disclosed is the array method of the word line drivers, which can reduce the pitch between the word line drivers so that the layout of the semiconductor memory array may be easily accomplished. Moreover, the array method of other components of the memory array is suggested.

REFERENCES:
patent: 4586171 (1986-04-01), Fujishima
patent: 4916661 (1990-04-01), Nawaki et al.
patent: 4977542 (1990-12-01), Matsuda et al.

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