Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-05-15
2007-05-15
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S678000
Reexamination Certificate
active
10902446
ABSTRACT:
Embodiments include interconnect of electrically conductive material with a contact surface, and a dielectric layer overlying the contact surface with a trench and via in the dielectric layer, the via extending to the contact surface. An interlock material is in the via with an interlock opening extending through the interlock material and into the interconnect. A layer of electroless material is on the base of the trench and the surfaces of the via, interlock material, and interlock opening. An subsequent interconnect is formed on the electroless material, in the trench, via, and interlock openings. The structure can be repeated to form a stack or column of interconnects that resist delamination.
REFERENCES:
patent: 5874358 (1999-02-01), Myers et al.
patent: 6492262 (2002-12-01), Uzoh
patent: 6642081 (2003-11-01), Patti
patent: 6946737 (2005-09-01), Sir et al.
Goh Eng Huat
Sir Jiun Hann
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen Tuan H.
LandOfFree
Interconnects with interlocks does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interconnects with interlocks, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnects with interlocks will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3774420