Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
2005-09-20
2005-09-20
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S774000, C257S776000, C257S773000
Reexamination Certificate
active
06946692
ABSTRACT:
An interconnection layout is provided. The interconnection layout includes a lower metal wiring layer (Metal—n) being drawn in a first direction; an upper metal wiring layer (Metal—n+1) being drawn in a 45-degree direction with respect to a second direction being normal to the first direction; and a first and second metal vias having different dimensions interposed between the lower metal wiring layer and the upper metal wiring layer for electrically connected the two metal wiring layers, and wherein the first metal via has the dimension that is larger than the dimension of the second metal via thereby compensating non-uniform current flowing through one of the two metal wiring layers.
REFERENCES:
patent: 5204542 (1993-04-01), Namaki et al.
patent: 5591998 (1997-01-01), Kimura et al.
patent: 6262487 (2001-07-01), Igarashi et al.
patent: 6291846 (2001-09-01), Ema et al.
patent: 6546540 (2003-04-01), Igarashi et al.
Clark Jasmine
Hsu Winston
United Microelectronics Corp.
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