Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-12-26
2006-12-26
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07155696
ABSTRACT:
The present invention relates to a method of interconnection routing for preventing crosstalk. The method comprises the following steps. Providing an aggressor connection path as a first net. Providing a victim connection path according to the requirements of a second net. Determining a voltage ramp time of the aggressor connection path, a victim total length of the victim connection path, a coupled wire length between the aggressor connection path and the victim connection path, and an equivalent load corresponding to the victim connection path. Evaluating a noise metric according to the voltage ramp time, the victim total length, the coupled wire length and the equivalent load. Modifying the victim connection path to shorten the coupled wire length if the noise metric is greater than a pre-determined value. Finally designating the victim connection path as the second net if the noise metric is less than the pre-determined value.
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patent: 6772403 (2004-08-01), Sasaki
Chen Bih-Cherng
Huang Hsing-Chien
Bowers Brandon W.
Chiang Jack
Taiwan Semiconductor Manufacturing Co. Ltd.
Thomas Kayden Horstemeyer & Risley
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