Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-05-29
2007-05-29
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S617000
Reexamination Certificate
active
10847409
ABSTRACT:
An interconnection pattern design, which has an improved reliability under mechanical shock and thermal cycling loads. A semiconductor component comprises a plurality of interconnections aligned into rows and columns to form an interconnection pattern, wherein the interconnections are aligned such that the pattern has substantially rounded or chamfered corners. The present invention provides an improved interconnection life and reliability of ball grid array packages and it is easily implemented.
REFERENCES:
patent: 5557502 (1996-09-01), Banerjee et al.
patent: 6274474 (2001-08-01), Caletka et al.
patent: 6291898 (2001-09-01), Yeh et al.
patent: 6444563 (2002-09-01), Potter et al.
patent: 6459161 (2002-10-01), Hirata et al.
patent: 6630737 (2003-10-01), Zhao et al.
patent: 6650014 (2003-11-01), Kariyazaki
patent: 6734544 (2004-05-01), Yan et al.
patent: 2003/0155640 (2003-08-01), Yan et al.
patent: 1 001 462 (2000-05-01), None
patent: 1 001 462 (2000-12-01), None
Cao Phat X.
Harrington & Smith PC
Nokia Corporation
LandOfFree
Interconnection pattern design does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Interconnection pattern design, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interconnection pattern design will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3731940