Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-06-26
2001-07-31
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S200000, C365S201000
Reexamination Certificate
active
06269040
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory devices, and more particularly relates to an interconnection network for connecting data and reference cells to sense amplifiers in a memory device.
2. Description of the Related Art
Dynamic random access memory (DRAM) is one type of semiconductor memory device which has been and is widely used. DRAMs are volatile. EEPROM (Electrically Erasable and Programmable Read Only Memory) is another type of semiconductor memory device which is not volatile. A disadvantage of EEPROM is its lower speed in read/write operation as compared to DRAMs.
Owing to recent advances in magnetic materials, magnetic random access memory (MRAM) has been developed as one of non-volatile memory devices which is capable of higher speed operations, especially in the read process. An MRAM device typically includes a plurality of memory cells arrayed on intersections of word lines and bit lines. Each cell of a MRAM device may be a type of magnetic tunnel junction (MTJ), which has two magnetic layers separated by an insulating layer. Data stored in memory cells of MTJ type may be represented as a direction of magnetic vectors in the magnetic layers, and the memory cells can hold the stored data until the direction of magnetic vectors is changed by signals externally applied to the memory cells. A typical MRAM array of MTJ type is described in the article entitled “A 10 ns Read Write Non-Volatile Memory Array using a Magnetic Tunnel Junction and FET Switch in Each Cell” by Roy Scheuerlein, et al., pp. 128-129, ISSCC 2000.
It is well known that, in high density memory devices, asymmetric network affects sense amplifiers in a memory device, which are used to detect states of memory cells each having a logic state “0” or “1”, or a state of similar magnitude. For example, noise sources can be unequally coupled to an asymmetric network connecting memory cells to sense amplifiers, thereby causing delay and/or disruption of signals being sensed in the amplifiers. In a dynamic sensing system, asymmetry in an interconnection network between sense amplifiers and memory array causes differences in load capacitance at the inputs of a sense amplifier. Such load capacitance difference in turn causes a delay in a transition of the sense amplifier either from “1” to “0” or from “0” to “1” (here, “0” and “1” are logic values). Thus, asymmetry in an interconnection network affects sensing speed of sense amplifiers. In an asymmetric interconnection network, the sensing of a valid state in a sense amplifier may also be degraded by coupling events from sources such as the substrate or neighboring metallic wires. An example of an asymmetric network is described in the article entitled “Non-Volatile RAM based on Magnetic Tunnel Junction Elements” by M. Durlam, et al., pp. 130-131, ISSCC 2000.
Thus, a need exists for a process for minimizing asymmetry in an interconnection network between memory cells and sense amplifiers in a memory device.
OBJECTS AND SUMMARY OF THE INVENTION
It is an object of the present invention to provide an interconnection network for connecting memory cells to sense amplifiers, wherein the interconnection network is symmetrically configured to prevent delay and to reduce noise associated with an asymmetric network.
It is another object of the present invention to provide an interconnection network for connecting memory cells to sense amplifiers, wherein an accurate reference signal is provided to the sense amplifier to enhance sensing operation of the sense amplifiers.
To attain the above and other objects and advantages, an interconnection network for connecting data and reference cells to sense amplifiers in a memory device according to the present invention, includes at least one sub-array having multiple memory cell columns and at least one reference cell column, wherein each memory cell column has a series of memory cells and each reference cell column has a series of reference cells; and at least one switch unit associated with the at least one sub-array, for selectively connecting the multiple memory cell columns to one of two inputs of a sense amplifier and selectively connecting the at least one reference cell column to the other of the two inputs of the sense amplifier, wherein the two inputs of the sense amplifier are substantially symmetric to each other such that each of the two inputs has substantially equal number of connections with the at least one switch unit. The at least one reference cell column has a series of reference cells, and each reference cell has a reference which has a mid-level value between a high and a low value of data in the memory cells. The at least one switch unit preferably includes switches each of which has a conduction path of which one end is connected to a corresponding memory cell column and the other end is connected to one of the two inputs of the sense amplifier; and at least one reference switch having a conduction path of which one end is connected to the at least one reference cell column and the other end is connected to the other of the two inputs of the sense amplifier, wherein the plurality of switches and the at least one reference switch are selectively switched under control of decoding signals externally applied. The two inputs of the sense amplifier each preferably have substantially equal number of connections with the switches and the at least one reference switch. The at least one switch unit may also include switches each of which has a conduction path of which one end is connected to a corresponding memory cell column and the other end is connected to one of the two inputs of the sense amplifier; and first and second reference switches having first and second conduction paths, respectively, the first conduction path connecting the at least one reference cell column to one of the two inputs and the second conduction path connecting the at least one reference cell column to the other of the two inputs of the sense amplifier, wherein the switches and the first and second reference switches are selectively switched under control of decoding signals externally applied. Each of the at least one sub-array may include first and second reference cell columns each having a series of reference cells, the first reference cell column having reference cells of logic high value and the second reference cell column having reference cells of logic low value, wherein the sense amplifiers are provided with a reference obtained from data of the logic high value and the logic low value stored in reference cells in the first and second reference cell columns, respectively. The at least one switch unit may also include switches each of which has a conduction path of which one end is connected to a corresponding memory cell column and the other end is connected to one of two inputs of a sense amplifier; and first and second reference switches having first and second conduction paths, respectively, the first conduction path connecting the first reference cell column to one of the two inputs and the second conduction path connecting the second reference cell column to the other of the two inputs of the sense amplifier, wherein the plurality of switches and the first and second reference switches are selectively switched under control of decoding signals externally applied. There may further provided a first connection unit for connecting first inputs of two sense amplifiers in response to a decoding signal externally applied; and a second connection unit for connecting second inputs of the two sense amplifiers in response to another decoding signal externally applied. Each of the two sense amplifiers preferably receives data from a selected memory cell via a first input and a reference via a second input, wherein the reference is obtained by averaging the logic high and low values of two selected reference cells in the first and second reference cell columns, respectively. The first inputs and the second inputs of the two sense amplifiers each have substantially equal number
Reohr William Robert
Scheuerlein Roy Edwin
International Business Machines - Corporation
Lam David
Nelms David
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