Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2005-09-06
2005-09-06
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C710S317000
Reexamination Certificate
active
06940308
ABSTRACT:
An interconnection network architecture which provides an interconnection network which is especially useful for FPGAs is described. Based upon Benes networks, the resulting network interconnect is rearrangeable so that routing between logic cell terminals is guaranteed. Upper limits on time delays for the network interconnect are defined and pipelining for high speed operation is easily implemented. The described network interconnect offers flexibility so that many design options are presented to best suit the desired application.
REFERENCES:
patent: 5299317 (1994-03-01), Chen et al.
patent: 5349248 (1994-09-01), Parlour et al.
patent: 5519629 (1996-05-01), Snider
patent: 5530813 (1996-06-01), Paulsen et al.
patent: 5987028 (1999-11-01), Yang et al.
patent: 6693456 (2004-02-01), Wong
patent: 0919938 (1999-06-01), None
patent: 03098353 (1991-04-01), None
Chan et al., “Architectural Tradeoffs in Field-Programmable-Device Based Computing Systems,” GPGAS for Custom Computing Machines, Procedings, IEEE Workshop on Napa, CA, USA, Apr. 5-7, 1993, pp. 152-161.
Aka Chan LLP
Chang Daniel
Leopard Logic Inc.
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