Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-12-15
2003-09-02
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S125000
Reexamination Certificate
active
06613605
ABSTRACT:
FIELD OF THE INVENTION
The invention is related to methods of forming bumped substrates with protuberances for inverted or flip-connection bonding of electronic devices including semiconductor devices, integrated circuits, and/or application specific integrated circuits and electromechanical devices.
BACKGROUND OF THE INVENTION
Pace, in U.S. Pat. Nos. 5,627,406, 5,793105, 5,866,441, 5,904,499 and 6,165,820 has disclosed electronic packaging modules for inverted bonding of electronic devices, semiconductor devices, integrated circuits and application specific integrated circuits, and methods of making the modules. The modules are characterized by a substrate or base having a conductive pattern with soft, ductile, metal protuberances on the conductive pattern; and the protuberances being capable of being metallurgically bonded to the input/output pads of electronic devices. In the examples Pace describes an electroplating method of forming rounded gold protuberances. The plating conditions must be tightly controlled in order to prevent nodular deposits, or lateral growth of the gold deposits (i.e. short circuits between protuberances).
SUMMARY OF THE INVENTION
The present invention is an improved method of connecting to electronic devices by means of metal protuberances protruding from a supporting substrate. The improvement comprises forming the metal protuberances by depositing a metal on areas of the substrate that contain metallic sites; melting the metal into the shape of convex protuberances, and bonding the protuberances to said device.
In one embodiment it is a method for connecting to an electronic device by providing an insulating base with a conductive pattern and the conductive pattern has contact areas wettable by a molten metal. The metal is deposited over the contact areas, and then melted. The molten metal forms into protuberances on the contact areas. The device is then connected to the conductive pattern by bonding the protuberances to the device.
The present invention is an improved method of forming bumped substrates having metal protuberances suitable for bonding to the input/out pads (I/O's) of semiconductor, electronic and miniature electromechanical devices. The substrates have a conductive pattern. The conductive pattern includes basis metal pads which correspond to the I/O's of the devices. The method comprises applying a metal suitable both for supporting the devices and for bonding the I/O's of the devices to contact areas of the basis metal pads of the substrate and then melting the metal to form protuberances on the basis metal pads.
In one aspect the invention is an improvement in a method of manufacturing a package suitable for packaging at least one semiconductor device. The package comprises a ring frame bonded between an insulating substrate and a cover, the insulating substrate having a conductive pattern and the conductive pattern having both contact pads for connecting to the semiconductor device and connections suitable for connecting the package to another assembly. The semiconductor device is mounted on the inside of the cover and the input/out pads (I/O's) of the semiconductor device are joined to the contact pads of the substrate, by metal protuberances protruding from the contact pads of the substrate. The improvement in the method comprises forming the protuberances by applying a metal over the contact pads of the conductive pattern of the substrate and then raising the temperature of substrate above the melting point the metal; the molten metal drawing back into protuberances on the contact pads, and then cooling the substrate.
REFERENCES:
patent: 5627406 (1997-05-01), Pace
patent: 5793105 (1998-08-01), Pace
patent: 5866441 (1999-02-01), Pace
patent: 5904499 (1999-05-01), Pace
patent: 6107120 (2000-08-01), Ohtsuka
patent: 6165820 (2000-12-01), Pace
patent: 6258703 (2001-07-01), Cotte et al.
Pace, U.S. Application No 09/737,407, filed Dec. 15, 2000 Title: “High Density Electronic Interconnection”.
Pace, U.S. Application No. 09/745,966, filed Dec. 22, 2000 Title: “Inverted Chip Bonded Module”.
Elms Richard
McCormack John F.
Owens Beth E.
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