Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration
Reexamination Certificate
1999-06-17
2002-07-16
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
C713S002000, C712S028000, C709S241000
Reexamination Certificate
active
06421775
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to data processing and, in particular, to a non-uniform memory access (NUMA) data processing system. Still more particularly, the present invention relates to a collection of interconnected processing nodes that may be configured as one or more data processing systems including at least one NUMA data processing system.
2. Description of the Related Art
It is well-known in the computer arts that greater computer system performance can be achieved by harnessing the processing power of multiple individual processors in tandem. Multi-processor (MP) computer systems can be designed with a number of different topologies, of which various ones may be better suited for particular applications depending upon the performance requirements and software environment of each application. One of the common MP computer topologies is a symmetric multi-processor (SMP) configuration in which multiple processors share common resources, such as a system memory and input/output (I/O) subsystem, which are typically coupled to a shared system interconnect. Such computer systems are said to be symmetric because all processors in an SMP computer system ideally have the same access latency with respect to data stored in the shared system memory.
Although SMP computer systems permit the use of relatively simple inter-processor communication and data sharing methodologies, SMP computer systems have limited scalability. In other words, while performance of an SMP s computer system can generally be expected to improve with scale (i.e., with the addition of more processors), inherent bus, memory, and input/output (I/O) bandwidth limitations prevent significant advantage from being obtained from scaling a SMP beyond an implementation-dependent size at which the utilization of these shared resources is optimized. Thus, the SMP topology itself suffers to a certain extent from bandwidth limitations, especially at the system memory, as the system scale increases. SMP computer systems also do not scale well from the standpoint of manufacturing efficiency. For example, although some components can be optimized for use in both uniprocessor and small-scale SMP computer systems, such components are often inefficient for use in large-scale SMPs. Conversely, components designed for use in large-scale SMPs may be impractical for use in smaller systems from a cost standpoint.
As a result, there has recently been increased interest in an MP computer system topology known as non-uniform memory access (NUMA), which addresses many of the limitations of SMP computer systems at the expense of some additional complexity. A typical NUMA computer system includes a number of interconnected nodes that each include one or more processors and a local “system” memory. Such computer systems are said to have a non-uniform memory access because each processor has lower access latency with respect to data stored in the system memory at its local node than with respect to data stored in the system memory at a remote node. NUMA systems can be further classified as either non-coherent or cache coherent, depending upon whether or not data coherency is maintained between caches in different nodes. The complexity of cache coherent NUMA (CC-NUMA) systems is attributable in large measure to the additional communication required for hardware to maintain data coherency not only between the various levels of cache memory and system memory within each node but also between cache and system memories in different nodes. NUMA computer systems do, however, address the scalability limitations of conventional SMP computer systems since each node within a NUMA computer system can be implemented as a smaller uniprocessor or SMP system. Thus, the shared components within each node can be optimized for use by one or a few processors, while the overall system benefits from the availability of larger scale parallelism while maintaining relatively low latency.
The present invention recognizes that the expense of a large-scale NUMA data processing system is difficult to justify in certain computing environments, such as those having varying workloads. That is, some computing environments infrequently require the processing resources of a large-scale NUMA data processing system to execute a single application and frequently require multiple smaller data processing systems to run different operating systems and/or different applications. Prior to the present invention, the varying workloads of such computing environments could be accommodated only by multiple computer systems of differing scale or by physically reconfiguring a NUMA system by connecting and disconnecting nodes as needed.
SUMMARY OF THE INVENTION
To address the above-described shortcomings in the art, the present invention provides a data processing system including a plurality of processing nodes that each contain at least one processor and data storage. The plurality of processing nodes are coupled together by a system interconnect. The data processing system further includes a configuration utility residing in data storage within at least one of the plurality of processing nodes. The configuration utility selectively configures the plurality of processing nodes into either a single non-uniform memory access (NUMA) system or into multiple independent data processing systems through communication via the system interconnect.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
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Brock Bishop Chapman
Glasco David Brian
Peterson James Lyle
Rajamony Ramakrishnan
Rockhold Ronald Lynn
Bracewell & Patterson L.L.P.
Cao Chu
Gaffin Jeffrey
Salys Casimer K.
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