Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-04-30
2002-02-05
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06345380
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to integrated semiconductor circuits, and more particularly to a plurality of interconnected integrated semiconductor circuits and chips in a microprocessor arranged to have reduced inductance during switching of one or more of the circuits and to a method for interconnecting such circuits and chips such that the inductance of the switched circuits will be reduced.
BACKGROUND OF THE INVENTION
Modem computers utilize large numbers of semiconductor chips that include logic circuits such as AND, OR, NAND, NOR, etc. Because of the large numbers of logic circuits required in modern computers it is often necessary that a number of such logic circuit chips be used. Such logic circuit chips typically include a plurality of logic circuits each of which is provided with a respective driver circuit and a respective Input/Output ( I/O ) circuit point or contact such as a pin or a pad. During operation of the computer many of these individual logic circuits in a chip are required by the computer processor to switch on simultaneously while other logic circuits in the same chips are held or remain off. As each required circuit switches on, an output current is applied to its respective I/O point. However, because each such I/O point has a load capacitance associated therewith, the current required to charge and discharge this load capacitance must flow from the driver power supply associated with the logic circuit being turned on. The driver power supply, so affected, further has some finite inductance associated with its power supply leads and the current required to charge and discharge the load capacitance connected to these I/O s points must necessarily also flow through this I/O point inductance in the I/O driver power supply lead. This inductance causes a change in the voltage at the I/O driver supply and creates a so-called voltage bounce proportional to the rate of change of the driver current and the supply inductance. If large numbers of drivers switch simultaneously and at high frequency, the resulting DC shift in the supply potential can degrade the noise margins on the chip. This becomes more significant as power supply voltages decrease.
There have been attempts in the past to control such a voltage noise or bounce in circuits.
In a paper entitled “Ground Bounce Control in CMOS Circuits” appearing in the “1988 IEEE International Solid State Circuits Conference Transactions,” the problem of ground noise or bounce, due to the variation of the chip ground relative to the external ground, was discussed together with a proposed solution. This solution required having a control voltage source, tailored to the process creating the devices in the circuit, for regulating the charge discharge rate of a series transistor in the output buffer and thereby equalizing the delay, speed, rise/fall time and ground bounce of the CMOS output buffers, thus slow the faster element. This proposed solution is process dependent and cannot, for a number of practical purposes, be used in production.
U.S. Pat. No. 5,317,206 is also directed to an attempt to stabilize the voltage bounce within a circuit and does so by adding delay elements to the circuit being controlled. These delay elements are arranged to decrease the rising speed of the voltage at the circuit output which prevents current from flowing abruptly from the power supply which, in turn, reduces the voltage noise but does do by sacrificing circuit speed.
Similarly U.S. Pat. No. 5,315,172 added a pair of transistors serially connected between the voltage supply and ground with their common terminal connected to the circuit output so that, when either one of this serially connected pair is turned on, a slower rate of charge or discharge of the output occurs. This slower rate of charge or discharge of the output reduces the time rate of change of current through the circuit inductance and thereby reduces the voltage noise or bounce but again does do by sacrificing circuit speed.
U.S. Pat. No. 5, 568,081 teaches the use of a variable slew rate control circuit for automatically adjusting the rate at which a node is driven to a voltage once again by sacrificing circuit speed.
This prior art did, of course, achieve an improvement in voltage noise or bounce but did so by introducing circuit elements which resulted in slower circuit performance times.
One of the hallmarks of the semiconductor industry has been and remains a demand for faster circuits, thus the industry will not accept any circuit changes that degrade the speed performance of the circuit. Therefore the industry will only accept, as a practical solution, a circuit change that will reduce voltage noise or voltage bounce that can be easily and inexpensively produced without sacrificing circuit speed or significantly impacting on other circuit performance criteria. Such a solution has long been sought by the industry without success.
The present invention achieves such a solution.
SUMMARY OF THE INVENTION
The present invention overcomes the above described problems encountered in reducing the problem of voltage noise or bounce in a computer during processor controlled activation or switching on of selected ones of the driver units in a computer and does so in a practical way without impacting on the performance or speed of the circuit being switched on.
Broadly this reduction in voltage bounce is achieved by forcing the Input/Output points, hereinafter referred to as I/O points, of static driver circuits, i.e., those driver circuits not being activated, to serve as alternative or additional voltage paths for the activated circuits.
The present invention accomplishes this by grouping the I/O points on the chips into logical, functional units such as data buses, control lines, power supply, etc.
In the present invention, the I/O points on a chip having a switched circuit, i.e., a circuit switched on at high frequency, and the I/O points on a chip having a static circuit, i.e., a circuit not switched on at high frequency, are selectively interconnected so that the switched circuit will be coupled to both its own local or on-chip power supplies and to the local or on-chip power supplies of a static circuit. By providing an alternate power supply path to the switched circuit, the inductance in the switched circuit and hence the voltage bounce is substantially reduced without adversely impacting on circuit speed.
This substantial reduction in induction and voltage bounce is achieved without adding circuit elements that will adversely alter the circuit speed.
The present invention thus relates to a system that includes a processor for selectively controlling a plurality of integrated circuit chips each of which is coupled to respective local or on-chip power supplies and to respective I/O points through one or more off chip drivers. One of the off chip drivers on each chip is provided with means, such as a latch, that will, when selected, interconnect the off chip driver circuits on the activated chip to the chip driver circuits local or on-chip power supplies on a different and inactive chip to reduce the inductance in the system and thereby reduce voltage bounce during the switching on of the activated chip.
The present invention is thus directed toward a method for interconnecting the first and second local or on-chip power supplies of a first chip, coupled to a first amplifier circuit coupled between a first integrated circuit and a first I/O signal path, to the first and second local or on-chip power supplies of a second chip, coupled to a second amplifier circuit coupled between a second integrated circuit and a second I/O signal path, to reduce the inductance between the first amplifier circuit and the first and second local or on-chip power supplies of the first chip during the activation or switching on of the first integrated circuit.
Accordingly, the present invention provides an improved integrated circuit system that has reduced noise bounce and inductance.
Further, the present invention provides an improved logic system that h
Bonaccio Anthony R.
Kalter Howard
Tonti William R.
Siek Vuthe
Smith Matthew
Thornton Francis J.
Walsh Robert A.
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